摘要:
A MMIC variable slope gain-equalizer varies the conductance of depletion mode Schottky gate FETs to controllably insert frequency dependent resonant members in a modified bridged-T configuration. Resistors connected from circuit input port to output port define the arms of the "T" and a T-node to which a first frequency dependent resonant member is connected in series with a first FET. A second FET and a second frequency dependent resonant member are each connected in series between the circuit ports, bridging the T. Preferably a third frequency dependent resonant member is series connected with the second frequency dependent member. Each frequency dependent resonant member resonates at about the highest frequency of interest, typically about 18 GHz. When the first FET is on and the second FET off, maximum attenuation at lower frequencies is inserted into the circuit, and when the first FET is off and the second FET on, minimum attenuation is inserted at lower frequencies. Intermediate levels of FET conductivity produce intermediate levels of frequency dependent attenuation. In a first embodiment, FET conductivity is controlled by two push-pull control voltages. A second embodiment uses a single control voltage to vary conductivity. The first embodiment operates at about 0-18 GHz, while the second embodiment operates at about 2-18 GHz. Each embodiment realizes a variable slope gain-versus frequency temperature function of between about -0.6 dB/GHz to about +0.2 dB/GHz with a 0 to +3VDC control voltage change.
摘要:
A MMIC variable att4enuator uses depletion mode Schottky gate FETS as variable conductance devices in a ".pi." configuration to vary attenuation as a function of a DC control voltage. Attenuation is flat within .+-.1 dB, VSWR is .ltoreq.2:1 throughout the operating frequency and control voltage range, and about 12 dB variable attenuation is provided. The ".pi." is formed by FETs in shunt to ground between attenuator input and output, and by a FET in series between input and output. Resistors and an inductor connected in parallel with the series FET extend attenuator bandwidth to 20 GHZ and improve attenuation linearity versus control voltage. A resistor in series with each shunt FET also improves linearity. The typically 0 to +3 VDC control voltage is applied to the FET gates and drain/source leads permitting attenuation control with a single control voltage. FR power capability is increased without degrading RF performance by using multi-gate FETs wherein the ratio of gate width to number of gates is maintained substantially constant compared to a single-gate FET. Series-connected FETs further increase attenuator RF power capability. Operating from 2-20 GHz, embodiments using a single control voltage handle about 30 mW RF input power and use single-gate and dual-gate FETs, and handle about 250 mW RF input power and use triple-gate FETs. A third embodiment, operating from DC-20 GHz and handling about 500 mW RF input power, employs dual-gate FETs throughout and requires two complementary control voltages.