FET monolithic microwave integrated circuit variable slope gain-equalizer
    1.
    发明授权
    FET monolithic microwave integrated circuit variable slope gain-equalizer 失效
    FET单片微波集成电路可变斜率增益均衡器

    公开(公告)号:US4967169A

    公开(公告)日:1990-10-30

    申请号:US388094

    申请日:1989-07-31

    摘要: A MMIC variable slope gain-equalizer varies the conductance of depletion mode Schottky gate FETs to controllably insert frequency dependent resonant members in a modified bridged-T configuration. Resistors connected from circuit input port to output port define the arms of the "T" and a T-node to which a first frequency dependent resonant member is connected in series with a first FET. A second FET and a second frequency dependent resonant member are each connected in series between the circuit ports, bridging the T. Preferably a third frequency dependent resonant member is series connected with the second frequency dependent member. Each frequency dependent resonant member resonates at about the highest frequency of interest, typically about 18 GHz. When the first FET is on and the second FET off, maximum attenuation at lower frequencies is inserted into the circuit, and when the first FET is off and the second FET on, minimum attenuation is inserted at lower frequencies. Intermediate levels of FET conductivity produce intermediate levels of frequency dependent attenuation. In a first embodiment, FET conductivity is controlled by two push-pull control voltages. A second embodiment uses a single control voltage to vary conductivity. The first embodiment operates at about 0-18 GHz, while the second embodiment operates at about 2-18 GHz. Each embodiment realizes a variable slope gain-versus frequency temperature function of between about -0.6 dB/GHz to about +0.2 dB/GHz with a 0 to +3VDC control voltage change.

    摘要翻译: MMIC可变斜率增益均衡器改变耗尽型肖特基栅极FET的电导,以可变地插入经修改的桥接T配置中的频率相关谐振元件。 从电路输入端口连接到输出端口的电阻器定义了与第一FET串联连接的第一频率相关谐振元件的“T”和T形节点的臂。 第二FET和第二频率相关谐振元件各自串联在电路端口之间,桥接T。优选地,第三频率相关谐振元件与第二频率依赖元件串联连接。 每个频率相关的谐振元件在大约最感兴趣的频率下谐振,通常约为18GHz。 当第一个FET导通并且第二个FET关闭时,较低频率的最大衰减被插入到电路中,当第一个FET关闭并且第二个FET导通时,在较低的频率插入最小的衰减。 中等水平的FET电导率产生中等水平的频率相关衰减。 在第一实施例中,FET电导率由两个推挽控制电压控制。 第二实施例使用单个控制电压来改变电导率。 第一实施例在约0-18GHz下工作,而第二实施例在约2-18GHz下工作。 每个实施例在0至+ 3VDC控制电压变化之间实现约-0.6dB / GHz至约+0.2dB / GHz的可变斜率增益对频率温度函数。

    FET monolithic microwave integrated circuit variable attenuator
    2.
    发明授权
    FET monolithic microwave integrated circuit variable attenuator 失效
    FET单片微波集成电路可变衰减器

    公开(公告)号:US4890077A

    公开(公告)日:1989-12-26

    申请号:US329625

    申请日:1989-03-28

    申请人: Horng-Jye Sun

    发明人: Horng-Jye Sun

    IPC分类号: H01P1/22

    CPC分类号: H01P1/227

    摘要: A MMIC variable att4enuator uses depletion mode Schottky gate FETS as variable conductance devices in a ".pi." configuration to vary attenuation as a function of a DC control voltage. Attenuation is flat within .+-.1 dB, VSWR is .ltoreq.2:1 throughout the operating frequency and control voltage range, and about 12 dB variable attenuation is provided. The ".pi." is formed by FETs in shunt to ground between attenuator input and output, and by a FET in series between input and output. Resistors and an inductor connected in parallel with the series FET extend attenuator bandwidth to 20 GHZ and improve attenuation linearity versus control voltage. A resistor in series with each shunt FET also improves linearity. The typically 0 to +3 VDC control voltage is applied to the FET gates and drain/source leads permitting attenuation control with a single control voltage. FR power capability is increased without degrading RF performance by using multi-gate FETs wherein the ratio of gate width to number of gates is maintained substantially constant compared to a single-gate FET. Series-connected FETs further increase attenuator RF power capability. Operating from 2-20 GHz, embodiments using a single control voltage handle about 30 mW RF input power and use single-gate and dual-gate FETs, and handle about 250 mW RF input power and use triple-gate FETs. A third embodiment, operating from DC-20 GHz and handling about 500 mW RF input power, employs dual-gate FETs throughout and requires two complementary control voltages.