公开(公告)号：US08861801B2

公开(公告)日：2014-10-14

申请号：US13418483

申请日：2012-03-13

申请人： Hiroshi Sukegawa ,  Osamu Yamaguchi

发明人： Hiroshi Sukegawa ,  Osamu Yamaguchi

IPC分类号： G06K9/00

CPC分类号： G06K9/00288 ,  G06K2009/00328

摘要： According to one embodiment, a facial image search system including attribute discrimination module configured to discriminate attribute based on facial feature extracted, a plurality of search modules configured to store facial feature as database in advance, add facial feature extracted to database, calculate degree of similarity between facial feature extracted and facial feature contained in database, setting module configured to generate setting information by associating with any attribute with information indicating search module, and control module configured to identify one or a plurality of search modules based on setting information and attribute and transmit facial feature extracted by feature extraction module to identified search modules.

摘要翻译： 根据一个实施例，一种面部图像搜索系统，包括：属性识别模块，被配置为基于提取的面部特征来区分属性;多个搜索模块，被配置为预先将面部特征存储为数据库;将数据库中提取的面部特征，计算相似度 在面部特征提取和数据库中包含的面部特征之间，设置模块被配置为通过与指示搜索模块的信息相关联的任何属性生成设置信息，以及控制模块，被配置为基于设置信息和属性来发送一个或多个搜索模块 特征提取模块提取的面部特征识别搜索模块。

公开(公告)号：US08443258B2

公开(公告)日：2013-05-14

申请号：US13531055

申请日：2012-06-22

申请人： Hiroshi Sukegawa

发明人： Hiroshi Sukegawa

IPC分类号： G11C29/00

CPC分类号： G06F13/385

摘要： A memory device includes a semiconductor memory including a plurality of memory cells, and a controller including a buffer which temporarily stores data, a data pattern check circuit which checks a predetermined data pattern of data that are stored in the buffer and are to be stored in a plurality of neighboring ones of the memory cells, and sends an address in accordance with a result of the check, and a data correction circuit which corrects a value of data at the address that is sent, and sends the corrected value to the semiconductor memory.

摘要翻译： 存储装置包括：包括多个存储单元的半导体存储器，以及包括临时存储数据的缓冲器的控制器，检查存储在缓冲器中并要存储在其中的数据的预定数据模式的数据模式检查电路 多个相邻的存储单元，并根据检查结果发送地址;以及数据校正电路，其对发送的地址上的数据值进行校正，并将校正后的值发送到半导体存储器 。

公开(公告)号：US20120320682A1

公开(公告)日：2012-12-20

申请号：US13598099

申请日：2012-08-29

申请人： Noboru SHIBATA ,  Hiroshi SUKEGAWA

发明人： Noboru SHIBATA ,  Hiroshi SUKEGAWA

IPC分类号： G11C16/10

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3459

摘要： A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.

摘要翻译： 通信线路连接到第一和第二芯片，并保持在第一信号电平。 监视电路将通信线路的信号电平从第一信号改变到第二信号电平，而第一和第二芯片中的一个使用大于参考电流的电流。 当通信线路的信号电平为第二信号电平时，第一和第二芯片中的另一个被控制为等待状态，该等待状态不转移到使用大于参考电流的电流的操作状态。

公开(公告)号：US08327067B2

公开(公告)日：2012-12-04

申请号：US13426782

申请日：2012-03-22

申请人： Yasuo Kudo ,  Hiroshi Sukegawa ,  Kazuya Kawamoto

发明人： Yasuo Kudo ,  Hiroshi Sukegawa ,  Kazuya Kawamoto

IPC分类号： G06F12/00

CPC分类号： G11C16/10

摘要： A nonvolatile memory system comprises a nonvolatile memory having a plurality of data areas; and a memory controller operative to control read and write operations to the nonvolatile memory. The memory controller successively executes read/write operations to plural sectors within a selected data area in the nonvolatile memory in accordance with a command and a sector count and sector address fed from a host device.

公开(公告)号：US20120266045A1

公开(公告)日：2012-10-18

申请号：US13531055

申请日：2012-06-22

申请人： Hiroshi SUKEGAWA

发明人： Hiroshi SUKEGAWA

IPC分类号： G06F12/02 ,  H03M13/05 ,  G06F11/10 ,  G06F12/00

CPC分类号： G06F13/385

摘要： A memory device includes a semiconductor memory including a plurality of memory cells, and a controller including a buffer which temporarily stores data, a data pattern check circuit which checks a predetermined data pattern of data that are stored in the buffer and are to be stored in a plurality of neighboring ones of the memory cells, and sends an address in accordance with a result of the check, and a data correction circuit which corrects a value of data at the address that is sent, and sends the corrected value to the semiconductor memory.

摘要翻译： 存储装置包括：包括多个存储单元的半导体存储器，以及包括临时存储数据的缓冲器的控制器，检查存储在缓冲器中并要存储在其中的数据的预定数据模式的数据模式检查电路 多个相邻的存储单元，并根据检查结果发送地址;以及数据校正电路，其对发送的地址上的数据值进行校正，并将校正后的值发送到半导体存储器 。

公开(公告)号：US20110246791A1

公开(公告)日：2011-10-06

申请号：US12880513

申请日：2010-09-13

申请人： Toru Kambayashi ,  Taku Kato ,  Hiroshi Sukegawa ,  Yoshihiko Hirose ,  Koichi Fujisaki

发明人： Toru Kambayashi ,  Taku Kato ,  Hiroshi Sukegawa ,  Yoshihiko Hirose ,  Koichi Fujisaki

IPC分类号： G06F12/14

CPC分类号： G06F12/1408 ,  G06F21/445 ,  G06F21/79 ,  G06F2221/2107

摘要： According to one embodiment, a memory chip, which is connected to a writing device that writes data and to a reading device that reads data, includes: a memory including a first area that is a predetermined data storage area; a second encryption key generating unit that receives second key information stored in the reading device and generates a third key; and a sending unit that transmits, to the reading device, second encrypted data obtained by encrypting data stored in the memory using the third key. The second encrypted data is received by the reading device and is decrypted by using a fourth key that is stored in the reading device and that corresponds to the third key.

摘要翻译： 根据一个实施例，连接到写入数据的写入装置和读取数据的读取装置的存储器芯片包括：存储器，包括作为预定数据存储区域的第一区域; 第二加密密钥生成单元，接收存储在读取装置中的第二密钥信息，生成第三密钥; 以及发送单元，其向所述读取装置发送通过使用所述第三密钥加密存储在所述存储器中的数据而获得的第二加密数据。 第二加密数据由读取装置接收，并且通过使用存储在读取装置中并对应于第三密钥的第四密钥进行解密。

公开(公告)号：US20110131470A1

公开(公告)日：2011-06-02

申请号：US12882979

申请日：2010-09-15

申请人： Toru KAMBAYASHI ,  Akihiro KASAHARA ,  Shinichi MATSUKAWA ,  Hiroyuki SAKAMOTO ,  Taku KATO ,  Hiroshi SUKEGAWA ,  Yoshihiko HIROSE ,  Atsushi SHIMBO ,  Koichi FUJISAKI

发明人： Toru KAMBAYASHI ,  Akihiro KASAHARA ,  Shinichi MATSUKAWA ,  Hiroyuki SAKAMOTO ,  Taku KATO ,  Hiroshi SUKEGAWA ,  Yoshihiko HIROSE ,  Atsushi SHIMBO ,  Koichi FUJISAKI

IPC分类号： G06F12/14 ,  H03M13/05 ,  G06F11/10

CPC分类号： G06F12/1466 ,  G06F21/30 ,  G06F21/79 ,  G06F2212/1052 ,  G06F2221/2107 ,  H04L9/08 ,  H04L9/0838 ,  H04L9/0897 ,  H04L2209/34 ,  H04L2463/062

摘要： According to one embodiment, a memory chip, which is connected to a controller that controls reading and writing of data in response to a request from an external device, includes: a memory including a special area that is a predetermined data storage area; a key storage unit that stores therein a second key that corresponds to a first key used by the external device to convert the data; a converting unit that receives, from the controller, data to be written into the special area and generates converted data by converting the data to be written using the second key; and a writing unit that writes the converted data into the special area.

摘要翻译： 根据一个实施例，连接到控制器的存储器芯片，其响应于来自外部设备的请求来控制数据的读取和写入，包括：存储器，包括作为预定数据存储区域的特殊区域; 密钥存储单元，其中存储与由外部设备用于转换数据的第一密钥相对应的第二密钥; 从所述控制器接收要写入所述特殊区域的数据并通过使用所述第二密钥转换要写入的数据来生成转换数据的转换单元; 以及将转换的数据写入特殊区域的写入单元。

公开(公告)号：US20110055466A1

公开(公告)日：2011-03-03

申请号：US12941710

申请日：2010-11-08

申请人： Yasuo KUDO ,  Hiroshi Sukegawa ,  Kazuya Kawamoto

发明人： Yasuo KUDO ,  Hiroshi Sukegawa ,  Kazuya Kawamoto

IPC分类号： G06F12/00 ,  G06F12/02

CPC分类号： G11C16/10

摘要： A nonvolatile memory system comprises a nonvolatile memory having a plurality of data areas; and a memory controller operative to control read and write operations to the nonvolatile memory. The memory controller successively executes read/write operations to plural sectors within a selected data area in the nonvolatile memory in accordance with a command and a sector count and sector address fed from a host device.

公开(公告)号：US07890732B2

公开(公告)日：2011-02-15

申请号：US11945187

申请日：2007-11-26

申请人： Hiroshi Sukegawa

发明人： Hiroshi Sukegawa

IPC分类号： G06F9/26 ,  G06F9/34

CPC分类号： G06F12/0246 ,  G11C16/102

摘要： A memory card includes a controller and a nonvolatile semiconductor memory. The controller manages a correspondence between a first address in a semiconductor memory of a first erase block size and a second address in a semiconductor memory of a second erase block size other than the first erase block size. The nonvolatile semiconductor memory is a memory of the second erase block size. The controller executes access to the nonvolatile semiconductor memory by the second address.

摘要翻译： 存储卡包括控制器和非易失性半导体存储器。 控制器管理第一擦除块大小的半导体存储器中的第一地址与第一擦除块大小之外的第二擦除块大小的半导体存储器中的第二地址之间的对应关系。 非易失性半导体存储器是第二擦除块大小的存储器。 控制器通过第二地址执行对非易失性半导体存储器的访问。

公开(公告)号：US20100217919A1

公开(公告)日：2010-08-26

申请号：US12551898

申请日：2009-09-01

申请人： Hiroshi Sukegawa ,  Hidetaka Tsuji ,  Shuji Takano

发明人： Hiroshi Sukegawa ,  Hidetaka Tsuji ,  Shuji Takano

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F2212/1032 ,  G11C16/349

摘要： A memory controller includes logical-physical address conversion table, an access number storing section configured to store the number of accesses to read out data from a memory cell in association with a logical address, a storage state checking section configured to check a storage state of data stored in the memory cell at every predetermined number of accesses, and a refresh processing section configured to perform refresh processing to restore the data stored in the memory cell if the storage state of the data is in a predetermined degraded state.

摘要翻译： 存储器控制器包括逻辑物理地址转换表，访问号码存储部，被配置为存储与逻辑地址相关联地从存储器单元读出数据的访问次数;存储状态检查部，被配置为检查存储状态 如果数据的存储状态处于预定的降级状态，则刷新处理部被配置为执行刷新处理以恢复存储在存储单元中的数据。