公开(公告)号：US20160276489A1

公开(公告)日：2016-09-22

申请号：US15168291

申请日：2016-05-31

Applicant: Kenichi OKAZAKI ,  Masatoshi YOKOYAMA ,  Masayuki SAKAKURA ,  Yukinori SHIMA ,  Yosuke KANZAKI ,  Hiroshi MATSUKIZONO ,  Takuya MATSUO ,  Yoshitaka YAMAMOTO

Inventor： Kenichi OKAZAKI ,  Masatoshi YOKOYAMA ,  Masayuki SAKAKURA ,  Yukinori SHIMA ,  Yosuke KANZAKI ,  Hiroshi MATSUKIZONO ,  Takuya MATSUO ,  Yoshitaka YAMAMOTO

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L21/02172 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78696

Abstract: An object is to suppress conducting-mode failures of a transistor that uses an oxide semiconductor film and has a short channel length. A semiconductor device includes a gate electrode 304, a gate insulating film 306 formed over the gate electrode, an oxide semiconductor film 308 over the gate insulating film, and a source electrode 310a and a drain electrode 310b formed over the oxide semiconductor film. The channel length L of the oxide semiconductor film is more than or equal to 1 μm and less than or equal to 50 μm. The oxide semiconductor film has a peak at a rotation angle 2θ in the vicinity of 31° in X-ray diffraction measurement.

Abstract translation: 目的是抑制使用氧化物半导体膜并具有短沟道长度的晶体管的导通模式故障。 半导体器件包括栅电极304，形成在栅电极上的栅极绝缘膜306，栅极绝缘膜上的氧化物半导体膜308以及形成在氧化物半导体膜上的源电极310a和漏电极310b。 氧化物半导体膜的沟道长度L大于等于1μm且小于等于50μm。 氧化物半导体膜在X射线衍射测定中具有在31°附近的旋转角度2θ的峰值。

公开(公告)号：US20140139775A1

公开(公告)日：2014-05-22

申请号：US14077390

申请日：2013-11-12

Applicant: Hiroyuki MIYAKE ,  Shunpei YAMAZAKI ,  Yoshifumi TANADA ,  Manabu SATO ,  Toshinari SASAKI ,  Kenichi OKAZAKI ,  Junichi KOEZUKA ,  Takuya MATSUO ,  Hiroshi MATSUKIZONO ,  Yosuke KANZAKI ,  Shigeyasu MORI

Inventor： Hiroyuki MIYAKE ,  Shunpei YAMAZAKI ,  Yoshifumi TANADA ,  Manabu SATO ,  Toshinari SASAKI ,  Kenichi OKAZAKI ,  Junichi KOEZUKA ,  Takuya MATSUO ,  Hiroshi MATSUKIZONO ,  Yosuke KANZAKI ,  Shigeyasu MORI

IPC: G02F1/1368 ,  H01L27/12

CPC classification number: H01L27/1225 ,  H01L27/124 ,  H01L29/78648

Abstract: A semiconductor device includes: a transistor including a gate electrode, a gate insulating film over the gate electrode, a semiconductor layer over the gate insulating film, and a source electrode and a drain electrode over the semiconductor layer; a first insulating film comprising an inorganic material over the transistor; a second insulating film comprising an organic material over the first insulating film; a first conductive film over the second insulating film and in a region overlapping with the semiconductor layer; a third insulating film comprising an inorganic material over the first conductive film; and a second conductive film over the third insulating film and in a region overlapping with the first conductive film. The absolute value of a first potential applied to the first conductive film is greater than the absolute value of a second potential applied to the second conductive film.

Abstract translation: 半导体器件包括：晶体管，包括栅极电极，栅极上的栅极绝缘膜，栅极绝缘膜上的半导体层，以及半导体层上的源极和漏极; 包括晶体管上的无机材料的第一绝缘膜; 包括在所述第一绝缘膜上的有机材料的第二绝缘膜; 在所述第二绝缘膜上并且在与所述半导体层重叠的区域中的第一导电膜; 在所述第一导电膜上包括无机材料的第三绝缘膜; 以及在所述第三绝缘膜上并且在与所述第一导电膜重叠的区域中的第二导电膜。 施加到第一导电膜的第一电位的绝对值大于施加到第二导电膜的第二电位的绝对值。

公开(公告)号：US20140022477A1

公开(公告)日：2014-01-23

申请号：US14009602

申请日：2012-04-02

Applicant: Hiroshi Matsukizono

Inventor： Hiroshi Matsukizono

IPC: G02F1/1362

CPC classification number: G02F1/136286 ,  G02F1/1368 ,  G02F2201/52

Abstract: There is provided a liquid crystal display panel that improves the reliability of thin film transistors while suppressing a degradation in display quality. A G TFT (120g) connected at its drain electrode (125d) to a G pixel electrode (130g) is disposed on the opposite side of the G pixel electrode (130g) from a B pixel electrode (130b). The distance between a B TFT (120b) connected at its drain electrode (125d) to the B pixel electrode (130b) and the B pixel electrode (130b) is greater than the distance between the G TFT (120g) connected at its drain electrode (125d) to the G pixel electrode (130g) and the G pixel electrode (130g). The distance between an R TFT (120r) connected at its drain electrode (125d) to an R pixel electrode (130r) and the B pixel electrode (130b) is greater than the distance between the B TFT (120b) connected to the B pixel electrode (130b) and the B pixel electrode (130b).

Abstract translation: 提供了一种在抑制显示质量下降的同时提高薄膜晶体管的可靠性的液晶显示面板。 在G像素电极（130g）的与B像素电极（130b）相反的一侧配置有在其漏电极（125d）与G像素电极（130g）连接的G TFT（120g）。 在其漏电极（125d）与B像素电极（130b）连接的B TFT（120b）与B像素电极（130b）之间的距离大于在其漏极连接的G TFT（120g）之间的距离 （125d）到G像素电极（130g）和G像素电极（130g）。 在其漏电极（125d）连接到R像素电极（130r）的R TFT（120r）与B像素电极（130b）之间的距离大于连接到B像素的B TFT（120b）之间的距离 电极（130b）和B像素电极（130b）。

公开(公告)号：US20130270554A1

公开(公告)日：2013-10-17

申请号：US13860879

申请日：2013-04-11

Applicant: Masatoshi YOKOYAMA ,  Tsutomu MURAKAWA ,  Kenichi OKAZAKI ,  Masayuki SAKAKURA ,  Takuya MATSUO ,  Yosuke KANZAKI ,  Hiroshi MATSUKIZONO ,  Yoshitaka YAMAMOTO

Inventor： Masatoshi YOKOYAMA ,  Tsutomu MURAKAWA ,  Kenichi OKAZAKI ,  Masayuki SAKAKURA ,  Takuya MATSUO ,  Yosuke KANZAKI ,  Hiroshi MATSUKIZONO ,  Yoshitaka YAMAMOTO

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/78696

Abstract: The semiconductor conductor device includes a gate electrode 106, an oxide semiconductor film 110, a source electrode 114a and a drain electrode 114b, and a channel region formed in the oxide semiconductor film. The channel region is formed between a first side surface 214a of the source electrode and a second side surface 214b of the drain electrode opposite to the first side surface 214a. The oxide semiconductor film has a side surface which overlaps with the gate electrode, which has a first high resistance region positioned between a first region 206a that is the nearest to one end 314a of the first side surface 214a and a second region 206b that is the nearest to one end 314b of the second side surface 214b. The first high resistance region has a corrugated side surface or the like.

Abstract translation: 半导体导体器件包括栅电极106，氧化物半导体膜110，源极114a和漏电极114b以及形成在氧化物半导体膜中的沟道区。 沟道区形成在源电极的第一侧表面214a和与第一侧表面214a相对的漏电极的第二侧表面214b之间。 氧化物半导体膜具有与栅电极重叠的侧面，该侧面具有位于最靠近第一侧面214a的一端314a的第一区域206a和位于第一侧面214a的一端314a的第一区域206a之间的第一高电阻区域， 最靠近第二侧表面214b的一端314b。 第一高电阻区域具有波纹状的侧面等。

公开(公告)号：US08212251B2

公开(公告)日：2012-07-03

申请号：US12531406

申请日：2008-02-29

Applicant: Yoshimizu Moriya ,  Mutsumi Nakajima ,  Yasuyoshi Kaise ,  Makoto Kita ,  Hiroshi Matsukizono ,  Yoshiyuki Itoh

Inventor： Yoshimizu Moriya ,  Mutsumi Nakajima ,  Yasuyoshi Kaise ,  Makoto Kita ,  Hiroshi Matsukizono ,  Yoshiyuki Itoh

IPC: H01L27/15

CPC classification number: H01L27/12 ,  G02F1/13624 ,  G02F1/1368 ,  H01L27/1277 ,  H01L29/78645 ,  H01L29/78696

Abstract: In an active-matrix substrate (100) according to the present invention, a semiconductor layer (110) has a first gettering region (112) adjacent to the source region (132) of a first thin-film transistor (130), a second gettering region (114) adjacent to the drain region (146) of a second thin-film transistor (140), and a third gettering region (116) adjacent to any of the source and drain regions located between the respective channel regions (134 and 144) of the first and second thin-film transistors (130 and 140) among the source and drain regions of the thin-film transistors included in the thin-film transistor element (120).

Abstract translation: 在根据本发明的有源矩阵基板（100）中，半导体层（110）具有与第一薄膜晶体管（130）的源极区域（132）相邻的第一吸杂区域（112），第二吸收区域 与第二薄膜晶体管（140）的漏极区域（146）相邻的吸杂区域（114）和位于各个沟道区域（134和134）之间的任何源极和漏极区域的第三吸杂区域（116） 包括在薄膜晶体管元件（120）中的薄膜晶体管的源极和漏极区域中的第一和第二薄膜晶体管（130和140）的第一和第二薄膜晶体管（144和144）。

公开(公告)号：US07968889B2

公开(公告)日：2011-06-28

申请号：US11997344

申请日：2006-07-24

Applicant: Hiroshi Matsukizono

Inventor： Hiroshi Matsukizono

IPC: G02F1/133

CPC classification number: H01L29/4908 ,  H01L21/02532 ,  H01L21/02675 ,  H01L29/66757 ,  H01L29/78675

Abstract: The present invention provides a semiconductor device having a high breakdown voltage and high reliability even if a gate electrode is formed to be thin. The present invention is a semiconductor device including a polycrystal semiconductor layer, a gate insulating film, and a gate electrode, stacked on an insulating substrate in this order, wherein the polycrystal semiconductor layer has a surface roughness of 9 nm or less, the gate insulating film has a multilayer structure including a silicon oxide film on the polycrystal semiconductor layer side and a film containing a material with a dielectric constant higher than a dielectric constant of silicon oxide on the gate electrode side.

Abstract translation: 本发明提供了即使栅电极形成较薄的具有高击穿电压和高可靠性的半导体器件。 本发明是依次层叠在绝缘基板上的多晶半导体层，栅极绝缘膜和栅电极的半导体装置，其中，多晶半导体层的表面粗糙度为9nm以下，栅极绝缘 膜具有包含多晶半导体层侧的氧化硅膜的多层结构和含有介电常数高于栅电极侧的氧化硅的介电常数的材料的膜。

公开(公告)号：US09349750B2

公开(公告)日：2016-05-24

申请号：US14077390

申请日：2013-11-12

Applicant: Hiroyuki Miyake ,  Shunpei Yamazaki ,  Yoshifumi Tanada ,  Manabu Sato ,  Toshinari Sasaki ,  Kenichi Okazaki ,  Junichi Koezuka ,  Takuya Matsuo ,  Hiroshi Matsukizono ,  Yosuke Kanzaki ,  Shigeyasu Mori

Inventor： Hiroyuki Miyake ,  Shunpei Yamazaki ,  Yoshifumi Tanada ,  Manabu Sato ,  Toshinari Sasaki ,  Kenichi Okazaki ,  Junichi Koezuka ,  Takuya Matsuo ,  Hiroshi Matsukizono ,  Yosuke Kanzaki ,  Shigeyasu Mori

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L27/124 ,  H01L29/78648

Abstract: A semiconductor device includes: a transistor including a gate electrode, a gate insulating film over the gate electrode, a semiconductor layer over the gate insulating film, and a source electrode and a drain electrode over the semiconductor layer; a first insulating film comprising an inorganic material over the transistor; a second insulating film comprising an organic material over the first insulating film; a first conductive film over the second insulating film and in a region overlapping with the semiconductor layer; a third insulating film comprising an inorganic material over the first conductive film; and a second conductive film over the third insulating film and in a region overlapping with the first conductive film. The absolute value of a first potential applied to the first conductive film is greater than the absolute value of a second potential applied to the second conductive film.

Abstract translation: 半导体器件包括：晶体管，包括栅极电极，栅极上的栅极绝缘膜，栅极绝缘膜上的半导体层，以及半导体层上的源极和漏极; 包括晶体管上的无机材料的第一绝缘膜; 包括在所述第一绝缘膜上的有机材料的第二绝缘膜; 在所述第二绝缘膜上并且在与所述半导体层重叠的区域中的第一导电膜; 在所述第一导电膜上包括无机材料的第三绝缘膜; 以及在所述第三绝缘膜上并且在与所述第一导电膜重叠的区域中的第二导电膜。 施加到第一导电膜的第一电位的绝对值大于施加到第二导电膜的第二电位的绝对值。

公开(公告)号：US09312278B2

公开(公告)日：2016-04-12

申请号：US14062085

申请日：2013-10-24

Applicant: Junichi Koezuka ,  Yukinori Shima ,  Yasuharu Hosaka ,  Kenichi Okazaki ,  Takuya Matsuo ,  Shigeyasu Mori ,  Yosuke Kanzaki ,  Hiroshi Matsukizono

Inventor： Junichi Koezuka ,  Yukinori Shima ,  Yasuharu Hosaka ,  Kenichi Okazaki ,  Takuya Matsuo ,  Shigeyasu Mori ,  Yosuke Kanzaki ,  Hiroshi Matsukizono

IPC: H01L27/12 ,  H01L27/32

CPC classification number: H01L27/1225 ,  H01L27/3262

Abstract: To improve the reliability of a transistor as well as to inhibit fluctuation in electric characteristics. A display device includes a pixel portion and a driver circuit portion outside the pixel portion; the pixel portion includes a pixel transistor, a first insulating film covering the pixel transistor and including an inorganic material, a second insulating film including an organic material over the first insulating film, and a third insulating film including an inorganic material over the second insulating film; and the driver circuit portion includes a driving transistor to supply a signal to the pixel transistor, the first insulating film covering the driving transistor, and the second insulating film over the first insulating film, and further includes a region in which the third insulating film is not formed over the second insulating film or a region in which the second insulating film is not covered with the third insulating film.

Abstract translation: 提高晶体管的可靠性以及抑制电特性的波动。 显示装置包括像素部分和像素部分外部的驱动器电路部分; 像素部分包括像素晶体管，覆盖像素晶体管并且包括无机材料的第一绝缘膜，在第一绝缘膜上的包括有机材料的第二绝缘膜，以及在第二绝缘膜上的包括无机材料的第三绝缘膜 ; 并且所述驱动电路部分包括驱动晶体管，用于向所述像素晶体管提供信号，所述第一绝缘膜覆盖所述驱动晶体管，并且所述第二绝缘膜在所述第一绝缘膜上方，并且还包括所述第三绝缘膜为 不形成在第二绝缘膜上或第二绝缘膜未被第三绝缘膜覆盖的区域。

公开(公告)号：US20140306220A1

公开(公告)日：2014-10-16

申请号：US14246493

申请日：2014-04-07

Applicant: Junichi KOEZUKA ,  Kenichi OKAZAKI ,  Masahiro TAKAHASHI ,  Takuya MATSUO ,  Shigeyasu MORI ,  Yosuke KANZAKI ,  Hiroshi MATSUKIZONO

Inventor： Junichi KOEZUKA ,  Kenichi OKAZAKI ,  Masahiro TAKAHASHI ,  Takuya MATSUO ,  Shigeyasu MORI ,  Yosuke KANZAKI ,  Hiroshi MATSUKIZONO

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L29/04 ,  H01L29/045 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/78696

Abstract: To provide a novel semiconductor device in which a reduction in channel length is controlled. The semiconductor device includes an oxide semiconductor layer having a crystal part, and a source electrode layer and a drain electrode layer which are in contact with the oxide semiconductor layer. The oxide semiconductor layer includes a channel formation region and an n-type region in contact with the source electrode layer or the drain electrode layer. The crystal orientation of the crystal part is different between the channel formation region and the n-type region.

Abstract translation: 提供控制通道长度减小的新型半导体器件。 半导体器件包括具有晶体部分的氧化物半导体层以及与氧化物半导体层接触的源电极层和漏电极层。 氧化物半导体层包括与源极电极层或漏极电极层接触的沟道形成区域和n型区域。 晶体部分的晶体取向在沟道形成区域和n型区域之间是不同的。

公开(公告)号：US20140306218A1

公开(公告)日：2014-10-16

申请号：US14244419

申请日：2014-04-03

Applicant: Junichi KOEZUKA ,  Masahiro KATAYAMA ,  Yukinori SHIMA ,  Kenichi OKAZAKI ,  Takuya MATSUO ,  Shigeyasu MORI ,  Yosuke KANZAKI ,  Hiroshi MATSUKIZONO

Inventor： Junichi KOEZUKA ,  Masahiro KATAYAMA ,  Yukinori SHIMA ,  Kenichi OKAZAKI ,  Takuya MATSUO ,  Shigeyasu MORI ,  Yosuke KANZAKI ,  Hiroshi MATSUKIZONO

IPC: H01L27/12 ,  H01L23/00

CPC classification number: H01L27/1225 ,  H01L23/3121 ,  H01L23/564 ,  H01L27/1248 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

Abstract: Variation in the electrical characteristics of transistors is minimized and reliability of the transistors is improved. A display device includes a pixel portion 104 and a driver circuit portion 106 outside the pixel portion. The pixel portion includes a pixel transistor, a first insulating layer 122 which covers the pixel transistor and includes an inorganic material, a second insulating layer 124 which is over the first insulating layer and includes an organic material, and a third insulating layer 128 which is over the second insulating layer and includes an inorganic material. The driver circuit portion includes a driving transistor for supplying a signal to the pixel transistor, and the first insulating layer covering the driving transistor. The second insulating layer is not formed in the driver circuit portion.

Abstract translation: 晶体管的电特性的变化最小化，晶体管的可靠性提高。 显示装置包括像素部分104和在像素部分外的驱动器电路部分106。 像素部分包括像素晶体管，覆盖像素晶体管并包括无机材料的第一绝缘层122，在第一绝缘层之上并包括有机材料的第二绝缘层124和第三绝缘层128 并且包括无机材料。 驱动器电路部分包括用于向像素晶体管提供信号的驱动晶体管，以及覆盖驱动晶体管的第一绝缘层。 第二绝缘层不形成在驱动电路部分中。