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    Process flow for capacitance enhancement in a DRAM trench
    2.
    发明授权
    Process flow for capacitance enhancement in a DRAM trench 失效
    DRAM沟槽中电容增强的工艺流程

    公开(公告)号：US06555430B1

    公开(公告)日：2003-04-29

    申请号：US09723420

    申请日：2000-11-28

    Applicant: Michael P. Chudzik ,  Johnathan Faltermeier ,  Rajarao Jammy ,  Stephan Kudelka ,  Irene McStay ,  Kenneth T. Settlemyer, Jr. ,  Helmut Horst Tews

    Inventor： Michael P. Chudzik ,  Johnathan Faltermeier ,  Rajarao Jammy ,  Stephan Kudelka ,  Irene McStay ,  Kenneth T. Settlemyer, Jr. ,  Helmut Horst Tews

    IPC: H01L218242

    CPC classification number: H01L27/1087 ,  H01L28/84 ,  Y10S438/964

    Abstract: Methods forming a trench region of a trench capacitor structure having increase surface area are provided. One method includes the steps of forming a discontinuous polysilicon layer on exposed walls of a lower trench region, the discontinuous polysilicon layer having gaps therein which expose portions of said substrate; oxidizing the lower trench region such that the exposed portions of said substrate provided by the gaps in the discontinuous polysilicon layer are oxidized into oxide material which forms a smooth and wavy layer with the discontinuous polysilicon layer; and etching said oxide material so as to form smooth hemispherical grooves on the walls of the trench region.

    Abstract translation: 提供了形成具有增加的表面积的沟槽电容器结构的沟槽区域的方法。 一种方法包括以下步骤：在下沟槽区域的暴露的壁上形成不连续的多晶硅层，所述不连续的多晶硅层在其中具有暴露所述衬底的部分的间隙; 氧化下沟槽区域，使得由不连续多晶硅层中的间隙提供的所述衬底的暴露部分被氧化成与不连续的多晶硅层形成平滑波浪层的氧化物材料; 并蚀刻所述氧化物材料，以在沟槽区域的壁上形成平滑的半球状凹槽。

    Process flow for sacrificial collar with polysilicon void
    3.
    发明授权
    Process flow for sacrificial collar with polysilicon void 有权
    具有多晶硅空隙的牺牲环的工艺流程

    公开(公告)号：US06544855B1

    公开(公告)日：2003-04-08

    申请号：US10041779

    申请日：2001-10-19

    Applicant: Helmut Horst Tews ,  Rolf Weis ,  Irene Lennox McStay

    Inventor： Helmut Horst Tews ,  Rolf Weis ,  Irene Lennox McStay

    IPC: H01L2120

    CPC classification number: H01L27/1087 ,  H01L27/10867

    Abstract: A process for forming a sacrificial collar on the top portion of a deep trench (114) of a semiconductor wafer (100). A nitride layer (116) is deposited within the trenches (114). A semiconductor material layer (120) is deposited over the nitride layer (116) and is etched back to a predetermined height (A) below the substrate 112 top surface. A semiconductor material plug (132) is formed at the top surface of the recessed semiconductor material layer (120), leaving a void (133) in the bottom of each trench (114). An oxide layer (134) and nitride layer (136) are formed over the wafer (100) and trenches (116), and the semiconductor material plug (132) and semiconductor material layer (120) are removed from the bottom of the trenches (116).

    Abstract translation: 一种用于在半导体晶片（100）的深沟槽（114）的顶部上形成牺牲套环的工艺。 氮化物层（116）沉积在沟槽（114）内。 半导体材料层（120）沉积在氮化物层（116）上并且被回蚀刻到衬底112顶表面下方的预定高度（A）。 半导体材料插塞（132）形成在凹陷半导体材料层（120）的顶表面处，在每个沟槽（114）的底部留下空隙（133）。 在晶片（100）和沟槽（116）之上形成氧化物层（134）和氮化物层（136），半导体材料插塞（132）和半导体材料层（120）从沟槽的底部 116）。

    Method of forming a vertically oriented device in an integrated circuit
    4.
    发明授权
    Method of forming a vertically oriented device in an integrated circuit 有权
    在集成电路中形成垂直取向器件的方法

    公开(公告)号：US06426253B1

    公开(公告)日：2002-07-30

    申请号：US09576465

    申请日：2000-05-23

    Applicant: Helmut Horst Tews ,  Alexander Michaelis ,  Brian S. Lee ,  Uwe Schroeder ,  Stephan Kudelka

    Inventor： Helmut Horst Tews ,  Alexander Michaelis ,  Brian S. Lee ,  Uwe Schroeder ,  Stephan Kudelka

    IPC: H01L218242

    CPC classification number: H01L27/10864 ,  H01L21/76237 ,  H01L21/823487 ,  H01L27/10841 ,  H01L27/10867

    Abstract: A system and method of forming an electrical connection (142) to the interior of a deep trench (104) in an integrated circuit utilizing a low-angle dopant implantation (114) to create a self-aligned mask over the trench. The electrical connection preferably connects the interior plate (110) of a trench capacitor to a terminal of a vertical trench transistor. The low-angle implantation process, in combination with a low-aspect ratio mask structure, generally enables the doping of only a portion of a material overlying or in the trench. The material may then be subjected to a process step, such as oxidation, with selectivity between the doped and undoped regions. Another process step, such as an etch process, may then be used to remove a portion of the material (120) overlying or in the trench, leaving a self-aligned mask (122) covering a portion of the trench, and the remainder of the trench exposed for further processing. Alternatively, an etch process alone, with selectivity between the doped and undoped regions, may be used to create the mask. The self-aligned mask then allows for the removal of selective portions of the materials in the trench so that a vertical trench transistor and a buried strap may be formed on only one side of the trench.

    Abstract translation: 使用低角度掺杂剂注入（114）在集成电路中形成到深沟槽（104）的内部的电连接（142）的系统和方法，以在沟槽上产生自对准掩模。 电连接优选地将沟槽电容器的内板（110）连接到垂直沟槽晶体管的端子。 低角度注入工艺与低纵横比掩模结构相结合，通常能够仅掺杂覆盖或在沟槽中的材料的一部分。 然后可以在掺杂区域和未掺杂区域之间选择性地对材料进行处理步骤，例如氧化。 然后可以使用诸如蚀刻工艺的另一工艺步骤来去除覆盖在沟槽中或在沟槽中的部分材料（120），留下覆盖沟槽的一部分的自对准掩模（122），并且其余部分 沟槽暴露进一步加工。 或者，可以使用仅在掺杂区域和未掺杂区域之间具有选择性的蚀刻工艺来产生掩模。 自对准掩模然后允许去除沟槽中的材料的选择性部分，使得可以仅在沟槽的一侧上形成垂直沟槽晶体管和掩埋带。

    Reduction of orientation dependent oxidation for vertical sidewalls of semiconductor substrates
    5.
    发明授权
    Reduction of orientation dependent oxidation for vertical sidewalls of semiconductor substrates 失效
    减少半导体衬底的垂直侧壁的取向依赖氧化

    公开(公告)号：US06362040B1

    公开(公告)日：2002-03-26

    申请号：US09501502

    申请日：2000-02-09

    Applicant: Helmut Horst Tews ,  Brian S. Lee ,  Ulrike Gruening ,  Raj Jammy ,  John Faltermeier

    Inventor： Helmut Horst Tews ,  Brian S. Lee ,  Ulrike Gruening ,  Raj Jammy ,  John Faltermeier

    IPC: H01L218242

    CPC classification number: H01L27/10864 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02299 ,  H01L21/31662 ,  H01L27/10876

    Abstract: A method for growing a dielectric layer on a substrate, in accordance with the present invention, includes the steps of providing a substrate having at least two crystallographic planes which experience different dielectric layer growth rates due to the at least two crystallographic planes. A first dielectric layer is grown on the at least two crystallographic planes such that the first dielectric layer has a first thickness on a first crystallographic plane and a second thickness on a second crystallographic plane. The first thickness is thicker than the second thickness for the first dielectric layer. Dopants are implanted through the first dielectric layer. A greater number of dopants are implanted in the substrate through the second thickness than through the first thickness of the first dielectric layer. The first dielectric layer is then removed. A second dielectric layer is grown at a same location as the removed first dielectric layer. The second dielectric layer has a first thickness on a first crystallographic plane and a second thickness on a second crystallographic plane. The first thickness and the second thickness of the second dielectric layer are closer in thickness than the first thickness and the second thickness of the first dielectric layer due to the implantation of the dopants.

    Abstract translation: 根据本发明的用于在衬底上生长电介质层的方法包括以下步骤：提供具有至少两个结晶面的衬底，所述晶体面由于至少两个晶面而具有不同的介电层生长速率。 在至少两个晶面上生长第一介电层，使得第一介电层在第一结晶平面上具有第一厚度，在第二结晶平面上具有第二厚度。 第一厚度比第一电介质层的第二厚度厚。 通过第一介电层注入掺杂剂。 通过第二厚度将更多数量的掺杂剂注入到衬底中，而不是通过第一介电层的第一厚度。 然后去除第一介电层。 在与去除的第一介电层相同的位置处生长第二介电层。 第二电介质层在第一结晶平面上具有第一厚度，在第二结晶平面上具有第二厚度。 由于掺杂剂的注入，第二介电层的第一厚度和第二厚度比第一厚度和第一介电层的第二厚度更厚。

    Integrated circuit vertical trench device and method of forming thereof
    7.
    发明授权
    Integrated circuit vertical trench device and method of forming thereof 有权
    集成电路垂直沟槽器件及其形成方法

    公开(公告)号：US06335247B1

    公开(公告)日：2002-01-01

    申请号：US09597389

    申请日：2000-06-19

    Applicant: Helmut Horst Tews ,  Alexander Michaelis ,  Stephan Kudelka ,  Uwe Schroeder ,  Brian S. Lee

    Inventor： Helmut Horst Tews ,  Alexander Michaelis ,  Stephan Kudelka ,  Uwe Schroeder ,  Brian S. Lee

    IPC: H01L21336

    CPC classification number: H01L27/10864 ,  H01L27/10876

    Abstract: A method of forming a vertically-oriented device in an integrated circuit using a selective wet etch to remove only a part of the sidewalls in a deep trench, and the device formed therefrom. While a portion of the trench perimeter (e.g., isolation collar 304) is protected by a mask (e.g., polysilicon 318), the exposed portion is selectively wet etched to remove selected crystal planes from the exposed portion of the trench, leaving a flat substrate sidewall (324) with a single crystal plane. A single side vertical trench transistor may be formed on the flat sidewall. A vertical gate oxide (e.g. silicon dioxide 330) of the transistor formed on the single crystal plane is substantially uniform across the transistor channel, providing reduced chance of leakage and consistent threshold voltages from device to device. In addition, trench widening is substantially reduced, increasing the device to device isolation distance in a single sided buried strap junction device layout.

    Abstract translation: 一种使用选择性湿蚀刻在集成电路中形成垂直取向器件的方法，以仅去除深沟槽中的一部分侧壁，以及由此形成的器件。 虽然沟槽周边的一部分（例如，隔离环304）被掩模（例如，多晶硅318）保护，但是暴露部分被选择性地湿蚀刻以从沟槽的暴露部分移除所选择的晶面，留下平坦的衬底 侧壁（324）与单晶面。 单侧垂直沟槽晶体管可以形成在平坦侧壁上。 形成在单晶平面上的晶体管的垂直栅极氧化物（例如二氧化硅330）在晶体管沟道上基本上是均匀的，从而降低了泄漏的机会和从器件到器件的一致的阈值电压。 此外，沟槽加宽大大降低，从而在单面掩埋带接合器件布局中将器件增加到器件隔离距离。

    Method of forming self-limiting polysilicon LOCOS for DRAM cell
    8.
    发明授权
    Method of forming self-limiting polysilicon LOCOS for DRAM cell 失效
    DRAM单元形成自限多晶硅LOCOS的方法

    公开(公告)号：US06309924B1

    公开(公告)日：2001-10-30

    申请号：US09585898

    申请日：2000-06-02

    Applicant: Ramachandra Divakaruni ,  Jack Allan Mandelman ,  Irene Lennox McStay ,  Larry A. Nesbit ,  Carl John Radens ,  Helmut Horst Tews

    Inventor： Ramachandra Divakaruni ,  Jack Allan Mandelman ,  Irene Lennox McStay ,  Larry A. Nesbit ,  Carl John Radens ,  Helmut Horst Tews

    IPC: H01L218242

    CPC classification number: H01L27/10861 ,  H01L27/10867

    Abstract: A method of forming relatively thin uniform insulating collar in the storage trench of a storage trench DRAM cell. A DRAM trench is first formed in a silicon substrate. Then, a nitride liner is deposited on the silicon trench walls. The nitride liner may be deposited directly on the silicon walls or on an underlying oxide layer. A layer of amorphous silicon is then deposited over the nitride liner. A silicon nitride layer is deposited on the oxidized surface of the amorphous silicon. A resist is formed in the lower portion of the trench, and the exposed silicon nitride layer on top of the amorphous silicon is removed, leaving the upper portion of the amorphous silicon layer exposed. The upper portion of the layer of amorphous silicon is then oxidized so as to form a relatively thin, uniform collar along the entire circumference of the trench. The nitride liner underlying the amorphous silicon layer enhances the thickness uniformity of the amorphous silicon layer and thereby the uniformity of the resulting oxide collar. The nitride liner also acts to limit lateral oxidation of the silicon trench walls during oxidation of the amorphous silicon layer. The nitride liner underlying the collar is also effective in cell operation to control the cell charge at the collar-substrate interface.

    Abstract translation: 一种在存储沟槽DRAM单元的存储沟槽中形成相对薄的均匀绝缘环的方法。 首先在硅衬底中形成DRAM沟槽。 然后，氮化物衬垫沉积在硅沟槽壁上。 氮化物衬垫可以直接沉积在硅壁上或下面的氧化物层上。 然后将一层非晶硅沉积在氮化物衬垫上。 在非晶硅的氧化表面上沉积氮化硅层。 在沟槽的下部形成抗蚀剂，去除在非晶硅顶部的暴露的氮化硅层，留下非晶硅层的上部。 然后，非晶硅层的上部被氧化，以便沿沟槽的整个圆周形成相对较薄的均匀的环。 非晶硅层下面的氮化物衬垫增强了非晶硅层的厚度均匀性，从而提高了所得氧化物环的均匀性。 氮化物衬垫还用于在非晶硅层的氧化期间限制硅沟槽壁的横向氧化。 在套环下面的氮化物衬垫在电池操作中也有效地控制在衬套 - 衬底界面处的电池电荷。

    Process for improving the thickness uniformity of a thin layer in semiconductor wafer fabrication
    9.
    发明授权
    Process for improving the thickness uniformity of a thin layer in semiconductor wafer fabrication 有权
    用于改善半导体晶片制造中的薄层的厚度均匀性的方法

    公开(公告)号：US06235651B1

    公开(公告)日：2001-05-22

    申请号：US09395952

    申请日：1999-09-14

    Applicant: Martin Schrems ,  Helmut Horst Tews

    Inventor： Martin Schrems ,  Helmut Horst Tews

    IPC: H01L2131

    CPC classification number: H01L21/02238 ,  H01L21/02255 ,  H01L21/31662

    Abstract: A two-step progressive thermal oxidation process is provided to improve the thickness uniformity of a thin oxide layer in semiconductor wafer fabrication. A semiconductor wafer, e.g., of silicon, with a surface subject to formation of an oxide layer thereon but which is substantially oxide layer-free, is loaded, e.g., at room temperature, into an oxidation furnace maintained at a low loading temperature, e.g., of 400-600° C., and the wafer temperature is adjusted to a low oxidizing temperature, e.g., of 400-600° C., all while the wafer is under an inert, e.g., nitrogen, atmosphere. The wafer is then subjected to initial oxidation, e.g., in dry oxygen, at the low oxidizing temperature to form a uniform initial thickness oxide, e.g., silicon dioxide, layer, e.g., of up to 10 angstroms, on the surface, after which the furnace temperature is increased to a high oxidizing temperature, e.g., of 700-1200° C., while the wafer is under an inert atmosphere. The wafer is next subjected to final oxidation, e.g., in oxygen and/or water vapor, at the high oxidizing temperature to increase uniformly the oxide layer to a selective final thickness, e.g., of 20-100 angstroms, whereupon the resultant uniform final thickness oxide layer-containing wafer is recovered from the furnace.

    Abstract translation: 提供了两步逐步热氧化工艺以改善半导体晶片制造中薄氧化物层的厚度均匀性。 诸如硅的半导体晶片，具有在其上形成氧化物层但基本上不含氧化物层的表面，例如在室温下被加载到维持在低负载温度的氧化炉中，例如 ，400-600℃，并且将晶片温度调节至低氧化温度，例如400-600℃，同时晶片处于惰性，例如氮气氛下。 然后将晶片在低氧化温度下进行初始氧化，例如在干燥的氧气中，以在表面上形成均匀的初始厚度氧化物，例如二氧化硅，例如至多10埃的层，之后 炉温升高到高的氧化温度，例如700-1200℃，同时晶片处于惰性气氛。 接着在高氧化温度下将晶片进行最终氧化，例如在氧气和/或水蒸气中，以将氧化物层均匀地增加至选择性最终厚度，例如20-100埃，由此得到均匀的最终厚度 从炉中回收含氧化物层的晶片。

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