公开(公告)号：US07772100B2

公开(公告)日：2010-08-10

申请号：US11909446

申请日：2006-03-21

Applicant: Gilles Ferru ,  Serge Bardy

Inventor： Gilles Ferru ,  Serge Bardy

IPC: H01L21/74 ,  H01L29/868

CPC classification number: H01L21/223 ,  H01L21/2254 ,  H01L21/74 ,  H01L21/743

Abstract: A method of providing a region of doped semiconductor (40) which is buried below the surface of a semiconductor substrate (10) without the requirement of epitaxially deposited layers is provided. The method includes the steps of forming first and second trench portions (26,28) in a semiconductor substrate and then introducing dopant (100) into the trench portions and diffusing the dopant into the semiconductor substrate such that a region of doped semiconductor (40) is formed extending from the first trench portion to the second trench portion. A diffusion barrier, for example formed of two barrier trenches (16, 18), is provided in the substrate adjacent the doping trenches to inhibit lateral diffusion of dopant from the doping trenches so as to maintain an undoped region (30) above the region of doped semiconductor. Advantageously, the electrical properties of the buried layer can be adjusted by varying the depths and size/spacing of the doping trenches and diffusion barrier(s), and the doping and diffusion parameters. The doping trenches can later be filled with polysilicon to provide electrical contact to the buried doped region.

Abstract translation: 提供一种埋置在半导体衬底（10）的表面下方的掺杂半导体（40）的区域的方法，而不需要外延沉积层。 该方法包括以下步骤：在半导体衬底中形成第一和第二沟槽部分（26,28），然后将掺杂剂（100）引入沟槽部分并将掺杂剂扩散到半导体衬底中，使得掺杂半导体（40）的区域 形成为从第一沟槽部分延伸到第二沟槽部分。 例如由两个势垒沟槽（16,18）形成的扩散阻挡层设置在邻近掺杂沟槽的衬底中，以抑制掺杂剂从掺杂沟槽的横向扩散，以便将未掺杂的区域（30）保持在 掺杂半导体。 有利地，可以通过改变掺杂沟槽和扩散势垒的深度和尺寸/间距以及掺杂和扩散参数来调节掩埋层的电性能。 稍后可以用多晶硅填充掺杂沟槽以提供与掩埋掺杂区域的电接触。

公开(公告)号：US08564202B2

公开(公告)日：2013-10-22

申请号：US12740412

申请日：2008-10-28

Applicant: Gilles Ferru ,  Jacques Le Berre

Inventor： Gilles Ferru ,  Jacques Le Berre

IPC: H01J13/46

CPC classification number: H05B33/0845 ,  H05B33/0821 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: A LED package includes a LED die, and a memory device. The memory device is arranged for holding LED data information for driving the LED die. A LED driver arrangement includes a LED package as described above, a LED driver device and a microcontroller. The microcontroller is connected to the memory device for accessing the LED data information for driving the LED die and to the LED driver for sending an output flux settings signal. The LED driver device is connected to the LED die for providing a driving signal to the LED die, the driving signal being based on the output flux in package settings signal from the microcontroller.

Abstract translation: LED封装包括LED管芯和存储器件。 存储器件被布置成保持用于驱动LED管芯的LED数据信息。 LED驱动器装置包括如上所述的LED封装，LED驱动器器件和微控制器。 微控制器连接到存储器件，用于访问用于驱动LED管芯的LED数据信息和用于发送输出通量设置信号的LED驱动器。 LED驱动器设备连接到LED管芯，用于向LED管芯提供驱动信号，驱动信号基于来自微控制器的封装设置信号中的输出通量。

公开(公告)号：US08183574B2

公开(公告)日：2012-05-22

申请号：US12297267

申请日：2007-04-17

Applicant: Gilles Ferru

Inventor： Gilles Ferru

IPC: H01L27/15

CPC classification number: H01L25/167 ,  F21V29/70 ,  F21Y2115/10 ,  H01L23/3677 ,  H01L33/642 ,  H01L2224/16

Abstract: The present invention relates to an electronic device for providing improved heat transporting capability for protecting heat sensitive electronics and a method for producing the same. The present invention also relates to uses of the electronic device for various applications such as in LED lamps for signalizing, signage, automative and illumination applications or a display apparatus or any combinations thereof.

Abstract translation: 本发明涉及一种用于提供改善的热传导能力以保护热敏电子装置的电子设备及其制造方法。 本发明还涉及电子装置用于各种应用的用途，例如用于信号灯，标牌，自动和照明应用的LED灯或显示装置或其任何组合。

公开(公告)号：US20100244691A1

公开(公告)日：2010-09-30

申请号：US12740412

申请日：2008-10-28

Applicant: Gilles Ferru ,  Jacques Le Berre

Inventor： Gilles Ferru ,  Jacques Le Berre

IPC: F21V23/00 ,  H01J9/00

CPC classification number: H05B33/0845 ,  H05B33/0821 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: A LED package includes a LED die, and a memory device. The memory device is arranged for holding LED data information for driving the LED die. A LED driver arrangement includes a LED package as described above, a LED driver device and a microcontroller. The microcontroller is connected to the memory device for accessing the LED data information for driving the LED die and to the LED driver for sending an output flux settings signal. The LED driver device is connected to the LED die for providing a driving signal to the LED die, the driving signal being based on the output flux in package settings signal from the microcontroller.

Abstract translation: LED封装包括LED管芯和存储器件。 存储器件被布置成保持用于驱动LED管芯的LED数据信息。 LED驱动器装置包括如上所述的LED封装，LED驱动器器件和微控制器。 微控制器连接到存储器件，用于访问用于驱动LED管芯的LED数据信息和用于发送输出通量设置信号的LED驱动器。 LED驱动器设备连接到LED管芯，用于向LED管芯提供驱动信号，驱动信号基于来自微控制器的封装设置信号中的输出通量。

公开(公告)号：US20090279218A1

公开(公告)日：2009-11-12

申请号：US12297267

申请日：2007-04-17

Applicant: Gilles Ferru

Inventor： Gilles Ferru

IPC: H02H9/04 ,  H05K7/20 ,  C25D5/02 ,  C23F1/00 ,  B23K31/02

CPC classification number: H01L25/167 ,  F21V29/70 ,  F21Y2115/10 ,  H01L23/3677 ,  H01L33/642 ,  H01L2224/16

Abstract: The present invention relates to an electronic device for providing improved heat transporting capability for protecting heat sensitive electronics and a method for producing the same. The present invention also relates to uses of the electronic device for various applications such as in LED lamps for signalizing, signage, automative and illumination applications or a display apparatus or any combinations thereof.

Abstract translation: 本发明涉及一种用于提供改善的热传导能力以保护热敏电子装置的电子设备及其制造方法。 本发明还涉及电子装置用于各种应用的用途，例如用于信号灯，标牌，自动和照明应用的LED灯或显示装置或其任何组合。

公开(公告)号：US20080179613A1

公开(公告)日：2008-07-31

申请号：US11915629

申请日：2006-05-31

Applicant: Matthias Wendt ,  Gilles Ferru

Inventor： Matthias Wendt ,  Gilles Ferru

IPC: H01L33/00 ,  C23F1/00 ,  G02B7/182

CPC classification number: G02B1/02 ,  G02B27/0977 ,  H01L33/60 ,  H01L33/62 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention deals with a process for the manufacturing of reflecting optical barriers comprising silicon and useful in combination with light emitting devices, wherein the process comprises anisotropic wet etching of the silicon material in such a manner that the rate of etching along the crystallographic (111) plane of the silicon material is slower than the rate of etching along the (110) and (100) planes. The present invention further comprises a reflecting optical barrier useful in combination with light emitting devices and a system containing at least one light emitting device comprising a reflecting optical barrier.

Abstract translation: 本发明涉及一种用于制造包含硅并且与发光器件组合有用的反射光学屏障的方法，其中该方法包括以下方式对硅材料进行各向异性湿法蚀刻：沿着晶体学（111 ）平面比沿（110）面和（100）面的蚀刻速度慢。 本发明还包括与发光器件组合使用的反射光学屏障和包含至少一个包括反射光学屏障的发光器件的系统。

公开(公告)号：US20080277764A1

公开(公告)日：2008-11-13

申请号：US11909446

申请日：2006-03-21

Applicant: Gilles Ferru ,  Serge Bardy

Inventor： Gilles Ferru ,  Serge Bardy

IPC: H01L29/12 ,  H01L21/22

CPC classification number: H01L21/223 ,  H01L21/2254 ,  H01L21/74 ,  H01L21/743

Abstract: A method of providing a region of doped semiconductor (40) which is buried below the surface of a semiconductor substrate (10) without the requirement of epitaxially deposited layers is provided. The method includes the steps of forming first and second trench portions (26,28) in a semiconductor substrate and then introducing dopant (100) into the trench portions and diffusing the dopant into the semiconductor substrate such that a region of doped semiconductor (40) is formed extending from the first trench portion to the second trench portion. A diffusion barrier, for example formed of two barrier trenches (16, 18), is provided in the substrate adjacent the doping trenches to inhibit lateral diffusion of dopant from the doping trenches so as to maintain an undoped region (30) above the region of doped semiconductor. Advantageously, the electrical properties of the buried layer can be adjusted by varying the depths and size/spacing of the doping trenches and diffusion barrier(s), and the doping and diffusion parameters. The doping trenches can later be filled with polysilicon to provide electrical contact to the buried doped region.

Abstract translation: 提供一种埋置在半导体衬底（10）的表面下方的掺杂半导体（40）的区域的方法，而不需要外延沉积层。 该方法包括以下步骤：在半导体衬底中形成第一和第二沟槽部分（26,28），然后将掺杂剂（100）引入沟槽部分并将掺杂剂扩散到半导体衬底中，使得掺杂半导体（40）的区域 形成为从第一沟槽部分延伸到第二沟槽部分。 例如由两个势垒沟槽（16,18）形成的扩散阻挡层设置在邻近掺杂沟槽的衬底中，以抑制掺杂剂从掺杂沟槽的横向扩散，以便将未掺杂的区域（30）保持在 掺杂半导体。 有利地，可以通过改变掺杂沟槽和扩散势垒的深度和尺寸/间距以及掺杂和扩散参数来调节掩埋层的电性能。 稍后可以用多晶硅填充掺杂沟槽以提供与掩埋掺杂区域的电接触。