公开(公告)号：US06594094B2

公开(公告)日：2003-07-15

申请号：US10025001

申请日：2001-12-18

申请人： James W. Rae ,  William Bliss ,  Jonathan Ashley ,  Razmik Karabed ,  Stephen J. Franck ,  Fritz Mistlberger ,  Matthias Driller ,  Heinrich Stockmanns ,  Dominik Margraf

发明人： James W. Rae ,  William Bliss ,  Jonathan Ashley ,  Razmik Karabed ,  Stephen J. Franck ,  Fritz Mistlberger ,  Matthias Driller ,  Heinrich Stockmanns ,  Dominik Margraf

IPC分类号： G11B502

CPC分类号： G11B20/10055 ,  G11B5/012 ,  G11B5/09 ,  G11B5/59688 ,  G11B5/6076 ,  G11B20/10009 ,  G11B20/10037

摘要： An improved sampled amplitude read/write channel is provided. The system is an integrated Generalized Partial Response Maximum Likelihood (GPRML) read channel incorporating Read, Write, and Servo modes of operation. One implementation includes a 32/34 rate parity code and matched Viterbi detector, a 32 state Viterbi detector optimal parity processor, robust frame synchronization, self-adaptive equalization, thermal asperity detection and compensation, adaptive magneto-resistive asymmetry compensation, low latency interpolated timing recovery and programmable write precompensation.

摘要翻译： 提供了一种改进的采样幅度读/写通道。 该系统是集成了读，写和伺服操作模式的集成广义部分响应最大似然（GPRML）读通道。 一个实现包括32/34速率奇偶校验码和匹配维特比检测器，32状态维特比检测器最佳奇偶校验处理器，鲁棒帧同步，自适应均衡，热粗糙度检测和补偿，自适应磁阻不对称补偿，低延迟内插时序 恢复和可编程预写。

公开(公告)号：US5210506A

公开(公告)日：1993-05-11

申请号：US869474

申请日：1992-04-15

申请人： Rudolf Koch ,  Fritz Mistlberger

发明人： Rudolf Koch ,  Fritz Mistlberger

IPC分类号： H03F3/68 ,  H03F1/32 ,  H03F3/21 ,  H03F3/30 ,  H03K17/16

CPC分类号： H03F3/3022 ,  H03F1/3217 ,  H03F3/211 ,  H03F3/301 ,  H03F3/303 ,  H03F3/3059 ,  H03K17/167 ,  H03F2200/234 ,  H03F2200/432 ,  H03F2203/30048 ,  H03F2203/30063

摘要： An output buffer amplifier includes one end stage for small output capacities and one end stage for large output capacities. The end stages have outputs being connected to one another. A control stage is connected upstream of the end stage for small output capacities. The control stage has one input being triggered by a signal proportional to an input signal of the end stage for large output capacities and another input being triggered by a signal proportional to an output signal of the end stage for small output capacities.

摘要翻译： 输出缓冲放大器包括用于小输出容量的一个端级和用于大输出容量的一端。 终端具有彼此连接的输出。 控制级连接在终端的上游，用于小输出能力。 控制级具有一个输入，由与用于大输出容量的末级的输入信号成比例的信号触发，另一个输入由与用于小输出容量的末级的输出信号成比例的信号触发。

公开(公告)号：US5337009A

公开(公告)日：1994-08-09

申请号：US46124

申请日：1993-04-12

申请人： Rudolf Koch ,  Fritz Mistlberger

发明人： Rudolf Koch ,  Fritz Mistlberger

IPC分类号： H03F3/45

CPC分类号： H03F3/45076

摘要： An error amplifier includes a differential amplifier stage having two inputs and one output. An MOS transistor has a gate terminal connected to the output of the differential amplifier stage, a source terminal connected to a first supply potential and a drain terminal forming an output of the error amplifier. A diode is connected in the conducting direction between the drain terminal of the MOS transistor and a second supply potential.

摘要翻译： 误差放大器包括具有两个输入和一个输出的差分放大器级。 MOS晶体管具有连接到差分放大器级的输出的栅极端子，连接到第一电源电位的源极端子和形成误差放大器的输出的漏极端子。 在MOS晶体管的漏极端子和第二供电电位之间的导通方向上连接二极管。

公开(公告)号：US06661590B2

公开(公告)日：2003-12-09

申请号：US09865860

申请日：2001-05-25

申请人： Sasan Cyrusian ,  Stephen J. Franck ,  Sriharsha Annadore ,  Elmar Bach ,  Siegfried Hart ,  Thomas Blon ,  William G. Bliss ,  James Wilson Rae ,  Michael Ruegg ,  Ulrich Huewels ,  Fritz Mistlberger

发明人： Sasan Cyrusian ,  Stephen J. Franck ,  Sriharsha Annadore ,  Elmar Bach ,  Siegfried Hart ,  Thomas Blon ,  William G. Bliss ,  James Wilson Rae ,  Michael Ruegg ,  Ulrich Huewels ,  Fritz Mistlberger

IPC分类号： G11B509

CPC分类号： G11B5/02 ,  G11B5/012 ,  G11B20/10009

摘要： A method and apparatus for running an analog portion (162) of a read/write channel (108) from a highly regulated power supply (260). The apparatus includes an analog portion (162), a clock synthesizer (154), and a highly regulated power supply (260) connected to the analog portion (162) and the clock synthesizer (154). The analog portion (162) and the clock synthesizer (154) both comprise high voltage transistors which operate in a first voltage range and low voltage transistors which operate in a second voltage range, wherein the first voltage range is within the second voltage range. The highly regulated power supply (260) supplies power that is within the first voltage range to the analog portion (162) and the clock synthesizer (154). The method includes generating power that is within the first voltage range using the highly regulated power supply (260), and supplying the power to the analog portion (162) and the clock synthesizer (154).