公开(公告)号：US08436759B2

公开(公告)日：2013-05-07

申请号：US13123610

申请日：2009-10-05

Applicant: Konstantinos Doris ,  Erwin Janssen

Inventor： Konstantinos Doris ,  Erwin Janssen

IPC: H03M1/12

CPC classification number: H03M1/0614 ,  H03M1/1215 ,  H03M1/466

Abstract: This invention relates to Analog to Digital Converters (ADC) and, inter alia, to Time Interleaved ADCs and Successive Approximation Register (SAR) ADC's. In a conventional Time Interleaved ADC employing SAR ADC units, the input signal is processed through a track-and-hold circuit (T/H), and then through a buffer circuit, before the SAR ADC unit. There, by means of a comparator, the signal is compared with a Digital-to-Analog Converter (DAC) signal from the SAR logic. The buffer reduces the influence of capacitive loading and physical layout design on the SAR ADC input, but typically has a non-linear response and thus introduces distortion to the input signal. This can limit the ADC linearity, particularly for high-speed ADCs operating with low-supply voltages. An objective of the invention is to reduce or eliminate the effect of the buffer non-linearity. This is done in some embodiments by routing both the signals to the comparator through the same buffer circuit. In another embodiment the DAC signal is routed through a separate second buffer circuit. By use of a single buffer circuit, or where there is ideal matching of the buffer circuits in the latter embodiment, the distortion effects are completely eliminated; however, for practical imperfectly matched buffer circuits according to the latter embodiment, the gain and off-set mismatches can be accommodated through calibration of the buffers or, in suitable applications, through the DAC calibration.

Abstract translation: 本发明涉及模数转换器（ADC），尤其涉及时间交错ADC和连续近似寄存器（SAR）ADC。 在采用SAR ADC单位的常规时间交错ADC中，输入信号通过跟踪保持电路（T / H），然后通过缓冲电路在SAR ADC单元之前进行处理。 在这里，通过比较器将信号与来自SAR逻辑的数模转换器（DAC）信号进行比较。 缓冲器减小了电容负载和物理布局设计对SAR ADC输入的影响，但通常具有非线性响应，从而对输入信号引入失真。 这可能会限制ADC的线性度，特别是对于使用低电源电压运行的高速ADC。 本发明的目的是减少或消除缓冲器非线性的影响。 这在一些实施例中通过将信号通过相同的缓冲器电路路由到比较器来完成。 在另一个实施例中，DAC信号被路由通过单独的第二缓冲电路。 通过使用单个缓冲电路，或者在后面的实施例中存在缓冲电路的理想匹配的情况下，失真效应被完全消除; 然而，对于根据后一实施例的实际不完全匹配的缓冲器电路，增益和偏移不匹配可以通过缓冲器的校准或者在适当的应用中通过DAC校准来适应。

公开(公告)号：US20090287493A1

公开(公告)日：2009-11-19

申请号：US11915478

申请日：2006-05-16

Applicant: Erwin Janssen ,  Derk Reefman

Inventor： Erwin Janssen ,  Derk Reefman

IPC: G10L19/00 ,  H03M3/00 ,  H03M1/06

CPC classification number: H03M7/3006 ,  G10L19/167 ,  G11B20/10481 ,  G11B20/10527 ,  G11B20/1262 ,  G11B2020/00014 ,  G11B2020/00065 ,  G11B2020/10546 ,  G11B2020/1288 ,  G11B2220/2541 ,  G11B2220/2579 ,  H03M7/3028

Abstract: An audio coding scheme allowing PCM signal to lossless DSD signal expansion for next generation optical disc formats. The method of encoding an input DSD signal includes up-sampling a corresponding PCM signal to the DSD sample rate. Then a set of loop filter parameters for a noise-shaping loop of a sigma-delta modulator are generated, either using a random starting condition of the sigma-delta modulator or including synchronization parameters. This will allow a decoder to regenerate an almost perfect signal, but still it needs a correction signal to be able to bit identically regenerate the DSD input signal. Therefore, a correction signal is generated based on a difference between a sigma-delta modulated version of the up-sampled PCM signal and the input DSD signal, wherein the sigma-delta modulated version of the up-sampled PCM signal is obtained using the set of loop filter parameters. The correction signal may be adapted to be applied to the low bit PCM signal, to the up-sampled PCM signal or to the output bit stream. Finally, an expansion bit stream is generated where an encoded version of the set of loop filter parameters and an encoded version of the correction signal are included. The decoder can reproduce the original DSD signal based on the already available PCM signal and the described expansion bit stream. Thus, the coding scheme enables top quality audio with minimal storage overhead since the already available PCM signal is used in combination with an expansion bit stream. Since only an additional data stream is required to be stored on a disc, e.g. as part of an MPEG stream, DSD functionality is added to existing systems without causing compatibility problems.

Abstract translation: 音频编码方案允许PCM信号对下一代光盘格式的无损DSD信号扩展。 编码输入DSD信号的方法包括将对应的PCM信号上采样到DSD采样率。 然后，使用Σ-Δ调制器的随机起始条件或包括同步参数来生成Σ-Δ调制器的噪声整形环路的一组环路滤波器参数。 这将允许解码器重新生成几乎完美的信号，但是仍然需要一个校正信号以能够相同地重新生成DSD输入信号。 因此，基于上采样PCM信号的Σ-Δ调制版本与输入DSD信号之间的差产生校正信号，其中使用该集合获得上采样PCM信号的Σ-Δ调制版本 的环路滤波器参数。 校正信号可适用于低位PCM信号，上采样PCM信号或输出比特流。 最后，生成扩展位流，其中包括一组环路滤波器参数的编码版本和校正信号的编码版本。 解码器可以基于已经可用的PCM信号和所描述的扩展位流再现原始DSD信号。 因此，由于已经可用的PCM信号与扩展位流结合使用，所以编码方案实现了具有最小存储开销的顶级质量音频。 由于只需要另外的数据流来存储在盘上， 作为MPEG流的一部分，DSD功能被添加到现有系统中，而不会引起兼容性问题。

公开(公告)号：US07218263B2

公开(公告)日：2007-05-15

申请号：US10574442

申请日：2004-10-08

Applicant: Erwin Janssen ,  Derk Reefman

Inventor： Erwin Janssen ,  Derk Reefman

IPC: H03M1/12

CPC classification number: H03M7/3006 ,  H03M3/35 ,  H03M3/458 ,  H03M3/50 ,  H03M7/302

Abstract: A system (10) and method that generate bit-streams that result in higher compression gains. The system is akin to a normal 1-bit SDM. Internally, the system (10) tries to find the best possible bit sequence by tracing N possible solutions at every time instant. In an implementation, the system has N>I trellis path structures (20). Every path is used to track a possible output bitstream. The quality of a bitstream is determined by measuring the (frequency weighted) difference between input and output; it is this measure that is reduced or minimized.

公开(公告)号：US4301721A

公开(公告)日：1981-11-24

申请号：US141807

申请日：1980-04-21

Applicant: Karl-Heinz Liessen ,  Erwin Janssen

Inventor： Karl-Heinz Liessen ,  Erwin Janssen

IPC: B30B3/04 ,  D21G1/00 ,  D21G1/02 ,  F16C13/02 ,  F16C23/00 ,  F16C7/04 ,  F16C35/00

CPC classification number: D21G1/0226 ,  B30B3/04 ,  D21G1/002 ,  F16C13/02 ,  F16C23/00

Abstract: A roll-journal bearing mounting is provided by a movable bearing housing from which pistons rigidly extend in opposite directions into cylinders rigidly fixed against displacement. Introduction of pressurized fluid to the cylinders moves the bearing housing either way in the direction of the pistons and cylinders. Consequently, a roll journaled by bearings in the bearing housings of two of the mountings can be moved towards and from a counter roll to apply roll nip pressure. At the same time the rigidly extending pistons in their rigidly fixed cylinders also function to hold the journal loading in a right angular direction, eliminating the need for the use of separate devices for that purpose.

Abstract translation: 滚动轴颈轴承安装件由可动轴承壳体提供，活塞刚性地沿相反方向延伸到刚性地固定抵抗位移的气缸中。 将加压流体引入气缸将轴承壳体沿活塞和气缸的方向移动。 因此，通过两个安装件的轴承座中的轴承轴承的辊可以朝向和来自反向辊移动以施加辊隙压力。 同时，其刚性固定的圆柱体中的刚性延伸的活塞也起到将轴颈加载保持在正确的角度方向的作用，从而无需为此目的使用单独的装置。

公开(公告)号：US08626808B2

公开(公告)日：2014-01-07

申请号：US12600397

申请日：2008-05-27

Applicant: Erwin Janssen

Inventor： Erwin Janssen

IPC: G06F17/10

CPC classification number: H03D3/006 ,  H03H17/06 ,  H03H2017/0247 ,  H03H2218/04

Abstract: A digital signal processing circuit comprises a band selector (14) for selecting at least one sub-band from a frequency spectrum of a digital sampled input signal. The band selector (14) comprises a plurality of processing branches corresponding to respective phases and an adder (28a, 28b) for adding branch signals from the branches. Each branch comprises a sub-sampler (20a,b) for sub-sampling sample values of the input signal at the phase corresponding to the branch, a filter (24a,b) with a first FIR filter (32, 34), applied alternatingly to sets of even and to sets of odd samples from the subsampler (20a,b) and a second FIR filter (36, 38) applied to further sets of odd and even samples from the subsampler (20a,b) when the first FIR filter is applied to the even and odd sets respectively. Output samples from the first and second FIR filter (24a,b) are combined to form the branch signals of the branch, according to a changing combination pattern that changes cyclically as a function of sample position and depends on a phase for which the branch is used.

Abstract translation: 数字信号处理电路包括用于从数字采样输入信号的频谱中选择至少一个子带的频带选择器（14）。 带选择器（14）包括对应于各个相位的多个处理分支和用于从分支添加分支信号的加法器（28a，28b）。 每个分支包括用于在与分支相对应的相位处对输入信号的采样值进行子采样的子采样器（20a，b），具有第一FIR滤波器（32,34）的滤波器（24a，b），交替施加 以及当所述第一FIR滤波器（20a，b）被应用于来自所述二次采样器（20a，b）的另外的奇数和偶数样本集合时，来自所述二次采样器（20a，b）的偶数和一组奇数样本集合和第二FIR滤波器 分别应用于偶数和奇数集。 来自第一和第二FIR滤波器（24a，b）的输出样本被组合以形成分支的分支信号，根据作为样本位置的函数循环变化的变化的组合模式，并且取决于分支是 用过的。

公开(公告)号：US08433000B2

公开(公告)日：2013-04-30

申请号：US12516782

申请日：2007-11-28

Applicant: Gerrit Willem Den Besten ,  Erwin Janssen

Inventor： Gerrit Willem Den Besten ,  Erwin Janssen

IPC: H03D3/18 ,  H03D3/24

CPC classification number: H04L7/10 ,  H03L7/0991 ,  H03L2207/50 ,  H04L7/0331

Abstract: The invention relates to a circuit and method for receiving a signal of which—at the receiver end—the frequency is basically unknown. By sampling the data and deriving the frequency of the signal (or actually: the data rate of the data carried by the signal) and setting a phase locked loop in the receiver to the derived—estimated—circuit, the receiver can very quickly tune in to the frequency of the signal. Hence, no embedded or accompanying clock is required for the signal. Oversampling of the signal by the receiver front end is preferred, though.

Abstract translation: 本发明涉及一种用于接收信号的电路和方法，其中 - 在接收机端 - 频率基本上是未知的。 通过对数据进行采样并得出信号的频率（或实际上是由信号携带的数据的数据速率），并将接收机中的锁相环设置为导出的估计电路，接收机可以很快地调谐 到信号的频率。 因此，信号不需要嵌入或附带的时钟。 尽管如此，优选的是由接收器前端过采样信号。

公开(公告)号：US20100302082A1

公开(公告)日：2010-12-02

申请号：US12744693

申请日：2008-11-24

Applicant: Johannes Hubertus Antonius Brekelmans ,  Konstantinos Doris ,  Erwin Janssen

Inventor： Johannes Hubertus Antonius Brekelmans ,  Konstantinos Doris ,  Erwin Janssen

IPC: H03M1/00

CPC classification number: H04B1/12 ,  H04B1/18

Abstract: A device for receiving a RF signal (1; 21) with loop-through output (16) is provided. The device comprises: an input (3) receiving a RF input signal (2); an analog-digital converter (8) converting the RF input signal (2) to a digital signal (9); a digital signal processing unit (10) digitally processing the digital signal (9); a digital-analog converter (14) converting the processed digital signal (13) to a loop-through RF signal (15) corresponding to the RF input signal (2); and a loop-through output (16) outputting the loop-through RF signal (15).

Abstract translation: 提供了一种用于接收具有环通输出（16）的RF信号（1; 21）的装置。 该装置包括：接收RF输入信号的输入端（3）; 将所述RF输入信号（2）转换为数字信号（9）的模拟数字转换器（8）; 数字信号处理单元（10）数字处理数字信号（9）; 将经处理的数字信号（13）转换成对应于RF输入信号（2）的环通RF信号（15）的数模转换器（14）; 以及输出环通RF信号（15）的环路输出（16）。

公开(公告)号：US20100091921A1

公开(公告)日：2010-04-15

申请号：US12530880

申请日：2008-03-17

Applicant: Gerrit W. Den Besten ,  Erwin Janssen

Inventor： Gerrit W. Den Besten ,  Erwin Janssen

IPC: H04L7/00 ,  G06F1/26

CPC classification number: H04L7/0004 ,  H03L7/0891 ,  H03L7/189 ,  H04L7/0008 ,  H04L7/0091 ,  H04L7/0338

Abstract: A data communication system has a transmitter with a first clock-generation circuit, and a receiver with a second clock generation circuit. At least a specific one of the clock-generation circuits is powered-down between consecutive data bursts. The system expedites the starting up of operational use of the system upon a power-down of the specific clock-generation circuit. The system presets at a predetermined value an operational quantity of the specific clock-generation circuit at the starting up.

Abstract translation: 数据通信系统具有具有第一时钟发生电路的发射机和具有第二时钟发生电路的接收机。 至少一个特定的时钟发生电路在连续的数据脉冲串之间断电。 该系统在特定时钟发生电路断电时加速系统的运行使用的启动。 该系统在启动时将特定的时钟发生电路的操作量预定在预定值。

公开(公告)号：US08664979B2

公开(公告)日：2014-03-04

申请号：US13094978

申请日：2011-04-27

Applicant: Konstantinos Doris ,  Erwin Janssen ,  Anton Zanikopoulos ,  Alessandro Murroni

Inventor： Konstantinos Doris ,  Erwin Janssen ,  Anton Zanikopoulos ,  Alessandro Murroni

IPC: G11C27/02

CPC classification number: G11C27/02 ,  G11C27/024

Abstract: Various exemplary embodiments relate to a tracking system and method. The system includes a transistor switch having a gate node and a source node, a power source circuit connected to the gate node, and a bootstrapping circuit connected to the source node and to the gate node. The power source circuit charges the switch during a first tracking phase, and the bootstrapping circuit charges the switch during a second tracking phase.

Abstract translation: 各种示例性实施例涉及跟踪系统和方法。 该系统包括具有栅极节点和源节点的晶体管开关，连接到栅极节点的电源电路以及连接到源节点和栅极节点的自举电路。 电源电路在第一跟踪阶段期间对开关充电，并且自举电路在第二跟踪阶段对开关充电。

公开(公告)号：US20130033392A1

公开(公告)日：2013-02-07

申请号：US13558525

申请日：2012-07-26

Applicant: Claudio Nani ,  Erwin Janssen ,  Konstantinos Doris ,  Athon Zanikopoulos

Inventor： Claudio Nani ,  Erwin Janssen ,  Konstantinos Doris ,  Athon Zanikopoulos

IPC: H03M1/50 ,  H03M1/12

CPC classification number: H03M1/08 ,  H03M1/0692 ,  H03M1/462

Abstract: A non-binary successive approximation analogue to digital converter, for converting using successive conversion steps, is operable in first and second modes. The first and second modes have different noise properties and the converter is switched between the modes during the conversion process.

Abstract translation: 用于使用连续转换步骤进行转换的非二进制逐次逼近模数转换器可在第一和第二模式中操作。 第一和第二模式具有不同的噪声特性，并且转换器在转换过程中在模式之间切换。