公开(公告)号：US20110273947A1

公开(公告)日：2011-11-10

申请号：US12985191

申请日：2011-01-05

申请人： Eric CARMAN

发明人： Eric CARMAN

IPC分类号： G11C11/402

CPC分类号： G11C7/00 ,  G11C11/403 ,  G11C11/406 ,  H01L2924/0002 ,  H01L2924/00

摘要： Techniques for refreshing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for refreshing a semiconductor memory device may include applying a plurality of voltage potentials to a memory cell in an array of memory cells. Applying a plurality of voltage potentials to the memory cell may include applying a first voltage potential to a first region of the memory cell via a respective source line of the array. Applying a plurality of voltage potentials to the memory cells may also include applying a second voltage potential to a second region of the memory cell via a respective local bit line and a respective selection transistor of the array. Applying a plurality of voltage potentials to the memory cells may further include applying a third voltage potential to a respective word line of the array, wherein the word line may be spaced apart from and capacitively to a body region of the memory cell that may be electrically floating and disposed between the first region and the second region. Applying a plurality of voltage potentials to the memory cells may further include applying a fourth voltage potential to a third region of the memory cell via a respective carrier injection line of the array.

摘要翻译： 公开了用于刷新半导体存储器件的技术。 在一个特定示例性实施例中，可以实现这些技术，因为用于刷新半导体存储器件的方法可以包括将多个电压电位施加到存储器单元阵列中的存储器单元。 将多个电压电位施加到存储器单元可以包括经由阵列的相应源极线向存储器单元的第一区域施加第一电压电位。 将多个电压电位施加到存储器单元还可以包括经由相应的本地位线和阵列的相应选择晶体管将第二电压电位施加到存储器单元的第二区域。 将多个电压电位施加到存储器单元还可以包括将第三电压电位施加到阵列的相应字线，其中字线可以与存储器单元的体区间隔开并且电容地与电容器电连接 浮置并设置在第一区域和第二区域之间。 将多个电压电位施加到存储器单元还可以包括经由阵列的相应载体注入线将第四电压电位施加到存储器单元的第三区域。

公开(公告)号：US07933140B2

公开(公告)日：2011-04-26

申请号：US12244183

申请日：2008-10-02

申请人： Ping Wang ,  Eric Carman

发明人： Ping Wang ,  Eric Carman

IPC分类号： G11C11/24

CPC分类号： G11C11/4074 ,  G11C11/404 ,  G11C11/4085 ,  G11C2211/4016

摘要： Techniques for reducing a voltage swing are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for reducing a voltage swing comprising: a plurality of dynamic random access memory cells arranged in arrays of rows and columns, each dynamic random access memory cell including one or more memory transistors. The one or more memory transistors of the apparatus for reducing a voltage swing may comprise: a first region coupled to a source line, a second region coupled to a bit line, a first body region disposed between the first region and the second region, wherein the first body region may be electrically floating, and a first gate coupled to a word line spaced apart from, and capacitively coupled to, the first body region. The apparatus for reducing a voltage swing may also comprise a first voltage supply coupled to the source line configured to supply a first voltage and a second voltage to the source line, wherein a difference between the first voltage and the second voltage may be less than 3.5V.

摘要翻译： 公开了用于降低电压摆幅的技术。 在一个特定示例性实施例中，这些技术可以被实现为用于减小电压摆幅的装置，包括：以行和列排列的多个动态随机存取存储器单元，每个动态随机存取存储器单元包括一个或多个存储晶体管。 用于降低电压摆幅的装置的一个或多个存储晶体管可以包括：耦合到源极线的第一区域，耦合到位线的第二区域，设置在第一区域和第二区域之间的第一体区，其中 第一体区可以是电浮置的，并且第一栅极耦合到与第一体区间隔开并且电容耦合到第一体区的字线。 用于减小电压摆动的装置还可以包括耦合到源极线的第一电压源，其被配置为向源极线提供第一电压和第二电压，其中第一电压和第二电压之间的差可以小于3.5 五

公开(公告)号：US20100142294A1

公开(公告)日：2010-06-10

申请号：US12632394

申请日：2009-12-07

申请人： Eric Carman

发明人： Eric Carman

IPC分类号： G11C7/00 ,  H01L29/78 ,  H01L21/336

CPC分类号： G11C11/404 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/7841

摘要： A semiconductor device along with circuits including the same and methods of operating the same are described. The device includes an electrically floating body region and a gate disposed about a first portion of the body region. The device includes a source region adjoining a second portion of the body region, the second portion adjacent the first portion and separating the source region from the first portion. The device includes a drain region adjoining a third portion of the body region, the third portion adjacent the first portion and separating the drain region from the first portion, wherein the source and drain regions are opposing.

摘要翻译： 描述了包括其的电路的半导体器件及其操作方法。 该装置包括电浮动体区域和围绕身体区域的第一部分设置的门。 该装置包括与该区域的第二部分邻接的源极区域，该第二部分与该第一部分相邻并且将该源区域与该第一部分分离。 该器件包括与该区域的第三部分邻接的漏极区域，与第一部分相邻的第三部分，并且将该漏极区域与该第一部分分开，其中该源区域和漏极区域相对。

公开(公告)号：US20090141550A1

公开(公告)日：2009-06-04

申请号：US12371551

申请日：2009-02-13

申请人： Eric Carman

发明人： Eric Carman

IPC分类号： G11C11/34 ,  G11C7/00

CPC分类号： G11C7/1006 ,  G11C7/1048 ,  G11C11/404 ,  G11C11/4087 ,  G11C11/4093 ,  G11C2211/4016 ,  H01L21/84 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10879 ,  H01L27/1203 ,  H01L29/7841 ,  H01L29/785

摘要： A memory cell array and device having a memory cell array (i.e., an integrated circuit device, for example, a logic device (such as, a microcontroller or microprocessor) or a memory device (such as, a discrete memory)) including electrically floating body transistors in which electrical charge is stored in the body of the transistor, and techniques for reading, controlling and/or operating such memory cell array and such device. The memory cell array and device include a variable and/or programmable word length. The word length relates to the selected memory cells of a selected row of memory cells (which is determined via address data). In one embodiment, the word length may be any number of memory cells of a selected row which is less than or equal to the total number of memory cells of the selected row of the memory array. In one aspect, write and/or read operations may be performed with respect to selected memory cells of a selected row of the memory array, while unselected memory cells of the selected row are undisturbed.

摘要翻译： 具有存储单元阵列的存储单元阵列和器件（即，集成电路器件，例如逻辑器件（例如，微控制器或微处理器）或存储器件（例如，分立存储器））包括电浮置 其中电荷存储在晶体管的主体中的体晶体管，以及用于读取，控制和/或操作这种存储单元阵列和这种器件的技术。 存储单元阵列和器件包括可变和/或可编程的字长。 字长涉及所选行的存储器单元的选定存储单元（其通过地址数据确定）。 在一个实施例中，字长可以是所选行的任何数量的存储器单元，其小于或等于存储器阵列的所选行的存储器单元的总数。 在一个方面，可以针对存储器阵列的选定行的所选择的存储器单元执行写入和/或读取操作，而所选择的行的未选择的存储器单元是不受干扰的。

公开(公告)号：US20090080244A1

公开(公告)日：2009-03-26

申请号：US12212326

申请日：2008-09-17

申请人： Eric Carman ,  Mikhail Nagoga ,  Serguei Okhonin

发明人： Eric Carman ,  Mikhail Nagoga ,  Serguei Okhonin

IPC分类号： G11C11/34

CPC分类号： G11C11/4096 ,  G11C11/406 ,  G11C2211/4016 ,  G11C2211/4065

摘要： A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device can be refreshed within a single clock cycle.

摘要翻译： 描述了包括其的电路的半导体器件及其操作方法。 该器件包括一个包括一个晶体管的存储单元。 晶体管包括栅极，电浮体区域，以及邻近身体区域的源极区域和漏极区域。 存储在设备的存储单元中的数据可以在单个时钟周期内刷新。

公开(公告)号：US20080205114A1

公开(公告)日：2008-08-28

申请号：US12082020

申请日：2008-04-08

申请人： Richard Ferrant ,  Serguei Okhonin ,  Eric Carman ,  Michel Bron

发明人： Richard Ferrant ,  Serguei Okhonin ,  Eric Carman ,  Michel Bron

IPC分类号： G11C5/06

CPC分类号： G11C11/404 ,  G11C7/18 ,  G11C8/08 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4097 ,  G11C2211/4016 ,  G11C2211/4065 ,  H01L21/84 ,  H01L27/10802 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns. Each semiconductor dynamic random access memory cell includes a transistor having a source region, a drain region, a electrically floating body region disposed between and adjacent to the source region and the drain region, and a gate spaced apart from, and capacitively coupled to, the body region. Each transistor includes a first state representative of a first charge in the body region, and a second data state representative of a second charge in the body region. Further, each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row.

摘要翻译： 这里描述和说明了许多发明。 在第一方面，本发明涉及一种从数据读取和将数据写入存储器件的存储单元的存储器件和技术。 在这方面，在本发明的这个方面的一个实施例中，用于操作该装置的存储器件和技术使得最小化，减少和/或消除电荷泵送现象的衰弱影响。 本发明的该实施例采用最小化，减少和/或消除幅度和/或极性的转变的控制信号。 在另一个实施例中，本发明是一种包括存储阵列的半导体存储器件，该存储器阵列包括以行和列为矩阵排列的多个半导体动态随机存取存储器单元。 每个半导体动态随机存取存储单元包括晶体管，其具有源极区，漏极区，设置在源极区和漏极区之间且与源极区和漏极区相邻的电浮动体区域，以及与该区域和漏极区域间隔开并电容耦合的栅极 身体区域。 每个晶体管包括代表身体区域中的第一电荷的第一状态和代表身体区域中的第二电荷的第二数据状态。 此外，每排半导体动态随机存取存储器单元包括仅与相关行的半导体动态随机存取存储单元连接的相关联的源极线。

公开(公告)号：US20080165605A1

公开(公告)日：2008-07-10

申请号：US11650101

申请日：2007-01-05

申请人： David Fisch ,  Eric Carman

发明人： David Fisch ,  Eric Carman

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40615 ,  G11C2207/104 ,  G11C2211/4016 ,  G11C2211/4067

摘要： The embodiments described herein allow a system using a memory array, or the memory itself, to more efficiently control refresh intervals. This reduces standby current and the overhead associated with refresh operations. One embodiment includes a variable analog refresh signal generation circuit that initiates a refresh operation on one or more memory cells of a memory array. The circuit integrates a refresh timer element with an event signal generator such that a refresh interval as defined by the refresh timer element is changed when events are detected that may change the data retention time of one or more memory cells. In various embodiments, one or more of the circuits is placed to monitor an entire memory array, different sub-arrays, or different portions of different sub-arrays. This allows additional refresh operations to be closely tied to actual events, thus increasing overall efficiency.

摘要翻译： 这里描述的实施例允许使用存储器阵列或存储器本身的系统更有效地控制刷新间隔。 这减少了备用电流和与刷新操作相关的开销。 一个实施例包括可变模拟刷新信号产生电路，其启动对存储器阵列的一个或多个存储器单元的刷新操作。 电路将刷新定时器元件与事件信号发生器集成，使得当检测到可能改变一个或多个存储器单元的数据保持时间的事件时，刷新定时器元件定义的刷新间隔被改变。 在各种实施例中，放置一个或多个电路以监视整个存储器阵列，不同子阵列或不同子阵列的不同部分。 这允许额外的刷新操作与实际事件紧密相关，从而提高整体效率。

公开(公告)号：US07359229B2

公开(公告)日：2008-04-15

申请号：US11713284

申请日：2007-03-02

申请人： Richard Ferrant ,  Serguei Okhonin ,  Eric Carman ,  Michel Bron

发明人： Richard Ferrant ,  Serguei Okhonin ,  Eric Carman ,  Michel Bron

IPC分类号： G11C5/06 ,  G11C7/00

CPC分类号： G11C11/404 ,  G11C7/18 ,  G11C8/08 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4097 ,  G11C2211/4016 ,  G11C2211/4065 ,  H01L21/84 ,  H01L27/10802 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns. Each semiconductor dynamic random access memory cell includes a transistor having a source region, a drain region, a electrically floating body region disposed between and adjacent to the source region and the drain region, and a gate spaced apart from, and capacitively coupled to, the body region. Each transistor includes a first state representative of a first charge in the body region, and a second data state representative of a second charge in the body region. Further, each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row.

公开(公告)号：US07301838B2

公开(公告)日：2007-11-27

申请号：US11299590

申请日：2005-12-12

申请人： William Kenneth Waller ,  Eric Carman

发明人： William Kenneth Waller ,  Eric Carman

IPC分类号： G11C7/00

CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C7/14 ,  G11C11/4099 ,  G11C2211/4013 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/7841

摘要： A technique of, and circuitry for sampling, sensing, reading and/or determining the data state of a memory cell of a memory cell array (for example, a memory cell array having a plurality of memory cells which consist of an electrically floating body transistor). In one embodiment, sense amplifier circuitry is relatively compact and pitched to the array of memory cells such that a row of data may be read, sampled and/or sensed during a read operation. In this regard, an entire row of memory cells may be accessed and read during one operation which, relative to at least architecture employing multiplexer circuitry, may minimize, enhance and/or improve read latency and read access time, memory cell disturbance and/or simplify the control of the sense amplifier circuitry and access thereof. The sense amplifier circuitry may include write back circuitry to modify or “re-store” the data read, sampled and/or sensed during a read operation and/or a refresh operation in the context of a DRAM array. The sense amplifier circuitry of this embodiment restores and/or refreshes data in an entire row of volatile and/or destructive read type memory cells in parallel. This architecture may minimize, enhance and/or improve write back and read latency parameters, relative to at least architecture employing multiplexer circuitry. Also, data that has been read, sampled and/or sensed by the sense amplifier circuitry during a read operation may be modified before being written back to one or more of the memory cells of the selected row of the array of memory cells.

摘要翻译： 用于采样，感测，读取和/或确定存储器单元阵列的存储器单元的数据状态的技术和电路（例如，具有由电浮体晶体管组成的多个存储单元的存储单元阵列 ）。 在一个实施例中，感测放大器电路相对紧凑并且倾斜到存储器单元阵列，使得在读取操作期间可以读取，采样和/或感测一行数据。 在这方面，可以在一个操作期间访问和读取整行存储器单元，其相对于至少采用多路复用器电路的架构可以最小化，增强和/或改善读延迟和读访问时间，存储单元干扰和/或 简化了读出放大器电路的控制及其访问。 读出放大器电路可以包括写回电路，以在DRAM阵列的上下文中修改或“重新存储”在读取操作期间和/或刷新操作期间读取，采样和/或感测的数据。 该实施例的读出放大器电路并行地恢复和/或刷新整个易失性和/或破坏性读取型存储单元的行中的数据。 相对于至少采用多路复用器电路的架构，该架构可以最小化，增强和/或改进回写和读取延迟参数。 此外，读取操作期间由读出放大器电路读取，采样和/或感测的数据可以在被写回存储器单元阵列的选定行的一个或多个存储器单元之前被修改。

公开(公告)号：US20070187775A1

公开(公告)日：2007-08-16

申请号：US11703429

申请日：2007-02-07

申请人： Serguei Okhonin ,  Eric Carman ,  Mark-Eric Jones

发明人： Serguei Okhonin ,  Eric Carman ,  Mark-Eric Jones

IPC分类号： H01L29/76

CPC分类号： H01L29/7841 ,  G11C7/1006 ,  G11C7/16 ,  G11C11/404 ,  G11C11/565 ,  G11C2211/4016

摘要： There are many inventions described herein as well as many aspects and embodiments of those inventions, for example, multi-bit memory cell and circuitry and techniques for reading, writing and/or operating a multi-bit memory cell (and memory cell array having a plurality of such memory cells) having one or more electrically floating body transistors in which an electrical charge is stored in the body region of the electrically floating body transistor. The multi-bit memory cell stores more than one data bit (for example, two, three, four, five, six, etc.) and/or more than two data states (for example, three, four, five, six, etc. data or logic states. Notably, the memory cell array may comprise a portion of an integrated circuit device, for example, logic device (for example, a microprocessor) or a portion of a memory device (for example, a discrete memory).

摘要翻译： 这里描述的许多发明以及这些发明的许多方面和实施例，例如多位存储器单元以及用于读取，写入和/或操作多位存储器单元（以及具有 多个这样的存储单元）具有一个或多个电浮动体晶体管，其中电荷存储在电浮体晶体管的体区中。 多比特存储单元存储多于一个的数据位（例如，两个，三个，四个，五个，六个等等）和/或两个以上的数据状态（例如，三个，四个，五个，六个等等 值得注意的是，存储单元阵列可以包括集成电路器件的一部分，例如逻辑器件（例如，微处理器）或存储器件（例如，分立存储器）的一部分。