High linearity voltage to current conversion
    1.
    发明授权
    High linearity voltage to current conversion 有权
    高线性电压到电流转换

    公开(公告)号:US07915928B2

    公开(公告)日:2011-03-29

    申请号:US12115015

    申请日:2008-05-05

    申请人: Dejun Wang

    发明人: Dejun Wang

    IPC分类号: H03F3/45

    CPC分类号: G05F1/561

    摘要: A system and method for performing voltage to current conversion, the system comprising of a first set of devices that senses the input voltage signal through its input terminal and replicates said input voltage across a second set of devices which then converts said replicated input voltage signal to an output current signal; a third set of devices that transfers the output current signal to output terminals; a differential feedback loop comprising an amplifier positioned between a first one of the first set of devices and a first one of the third set of devices; and a common mode feedback loop that regulates the output average voltage to a reference voltage.

    摘要翻译: 一种用于执行电压到电流转换的系统和方法,所述系统包括通过其输入端感测输入电压信号的第一组装置,并且跨越第二组装置复制所述输入电压,然后将所述复制输入电压信号转换成 输出电流信号; 将输出电流信号传送到输出端的第三组装置; 差分反馈回路,包括位于所述第一组装置中的第一组和所述第三组装置中的第一组之间的放大器; 以及将输出平均电压调节到参考电压的共模反馈回路。

    Apparatus for and method of feature extraction for image recognition
    2.
    发明授权
    Apparatus for and method of feature extraction for image recognition 有权
    用于图像识别的特征提取的装置和方法

    公开(公告)号:US07715659B2

    公开(公告)日:2010-05-11

    申请号:US10893346

    申请日:2004-07-19

    IPC分类号: G06K9/54

    CPC分类号: G06K9/00248 G06K9/00288

    摘要: An apparatus for and method of performing a most informative feature extraction (MIFE) method in which a facial image is separated into sub-regions, and each sub-region makes individual contribution for performing facial recognition. Specifically, each sub-region is subjected to a sub-region based adaptive gamma (SadaGamma) correction or sub-region based histogram equalization (SHE) in order to account for different illuminations and expressions. A set of reference images is also divided into sub-regions and subjected to the SadaGamma correction or SHE. A comparison is made between the each corrected sub-region and each corresponding sub-region of the reference images. Based upon the comparisons made individually for the sub-regions of the facial image, one of the stored reference images having the greatest correspondence is chosen. While usable individually, using the MIFE and/or SadaGamma correction or SHE together achieves a lower error ratio in face recognition under different expressions, illuminations and occlusions.

    摘要翻译: 一种用于执行其中将面部图像分成子区域的最具信息特征提取(MIFE)方法的装置和方法,并且每个子区域对进行面部识别作出个人贡献。 具体地说,为了解决不同的照明和表达,每个子区域经历基于子区域的自适应伽马(SadaGamma)校正或基于子区域的直方图均衡(SHE)。 一组参考图像也被划分成子区域并进行SadaGamma校正或SHE。 在每个校正子区域和参考图像的每个相应子区域之间进行比较。 基于针对面部图像的子区域的单独比较,选择具有最大对应关系的所存储的参考图像之一。 虽然可以单独使用,但使用MIFE和/或SadaGamma校正或SHE一起可以在不同表达,照明和遮挡下的脸部识别中实现较低的误差比。

    High voltage electrostatic discharge clamp using deep submicron CMOS technology
    3.
    发明授权
    High voltage electrostatic discharge clamp using deep submicron CMOS technology 有权
    采用深亚微米CMOS技术的高压静电放电钳

    公开(公告)号:US08654490B2

    公开(公告)日:2014-02-18

    申请号:US13398638

    申请日:2012-02-16

    申请人: Dejun Wang

    发明人: Dejun Wang

    IPC分类号: H02H9/00

    CPC分类号: H01L27/0285 H02H9/046

    摘要: An ESD circuit includes a plurality of MOS devices arranged in a stack, wherein each of the MOS devices comprises a source, a drain, and a gate; a voltage source inputting a supply voltage to the stack of MOS devices; a first plurality of resistors dividing the supply voltage to each source and each drain of the MOS devices in the stack; a second plurality of resistors biasing the supply voltage to each gate of the MOS devices in the stack; an inverter device operatively connected to the second plurality of resistors; a time lag circuit that turns the inverter device on and off; and a plurality of capacitors pulling the voltage to each gate of the MOS devices in the stack to the supply voltage upon the inverter device turning off.

    摘要翻译: ESD电路包括布置在堆叠中的多个MOS器件,其中每个MOS器件包括源极,漏极和栅极; 电压源,向MOS器件堆叠输入电源电压; 第一多个电阻器,用于将电源电压划分为堆叠中的MOS器件的每个源极和每个漏极; 第二多个电阻器,用于将电源电压偏置到堆叠中的MOS器件的每个栅极; 可操作地连接到第二多个电阻器的逆变器装置; 一个使逆变器装置打开和关闭的时滞电路; 以及多个电容器,其将逆变器装置关闭时将堆叠中的MOS器件的各栅极的电压拉至电源电压。

    Continuous time sigma-delta analog-to-digital converter with stability
    4.
    发明授权
    Continuous time sigma-delta analog-to-digital converter with stability 有权
    具有稳定性的连续时间Σ-Δ模数转换器

    公开(公告)号:US07626527B1

    公开(公告)日:2009-12-01

    申请号:US12169763

    申请日:2008-07-09

    IPC分类号: H03M3/00

    CPC分类号: H03M3/366 H03M3/424

    摘要: A continuous time sigma-delta analog-to-digital converter (CT ΣΔADC) including an integrator, which includes an operational amplifier having at least one input terminal that receives an input signal, a feedback mechanism operatively connected to the operational amplifier, at least one capacitor coupled to the operational amplifier and the feedback mechanism, a reset switch coupled to the at least one capacitor, the operational amplifier, and the feedback mechanism, and a single directional voltage-to-current converter coupled to the input terminal. The single directional voltage-to-current converter translates a differential signal voltage only to a differential signal current. The reset switch resets the feedback mechanism. The single directional voltage-to-current converter behaves a one-directional resistor. The integrator prevents current generation when there is a non-linear disturbance at the input terminal of the operational amplifier. The single directional voltage-to-current converter clips an input current that exceeds a threshold value.

    摘要翻译: 包括积分器的连续时间Σ-Δ模数转换器(CT SigmaDeltaADC),其包括具有接收输入信号的至少一个输入端的运算放大器,可操作地连接到运算放大器的反馈机构,至少一个 耦合到运算放大器和反馈机构的电容器,耦合到至少一个电容器,运算放大器和反馈机构的复位开关,以及耦合到输入端子的单向电压 - 电流转换器。 单向电压 - 电流转换器将差分信号电压转换为差分信号电流。 复位开关复位反馈机制。 单向电压 - 电流转换器采用单向电阻器。 当在运算放大器的输入端处存在非线性干扰时,积分器防止电流产生。 单向电压 - 电流转换器将超过阈值的输入电流钳位。

    Low noise, low power, high linearity differential amplifier with a capacitive input impedance
    5.
    发明授权
    Low noise, low power, high linearity differential amplifier with a capacitive input impedance 有权
    低噪声,低功耗,高线性度差分放大器,具有电容性输入阻抗

    公开(公告)号:US07592870B2

    公开(公告)日:2009-09-22

    申请号:US11837638

    申请日:2007-08-13

    IPC分类号: H03F3/45

    摘要: A low noise, low power differential two-stage amplifier includes a first stage comprising a pair of electrical devices that sense an input signal difference across the pair of electrical devices; and a control feedback loop operatively connected to the first stage, wherein the first stage in combination with the control loop feedback is adapted to place an exact copy of the signal across a first pair of resistive components, wherein the first pair of resistive components are adapted to generate a differential signal current, wherein the control feedback loop is adapted to ensure that the differential signal current goes a second pair of resistive components to generate a voltage output. Preferably, the first and second pair of resistive components are in ratio to produce the exact copy of the signal with some gain at an output of the first stage.

    摘要翻译: 低噪声,低功率差分两级放大器包括:第一级,包括一对感测一对电气装置上的输入信号差的电气装置; 以及可操作地连接到第一级的控制反馈回路,其中结合控制回路反馈的第一级适于将信号的精确副本放置在第一对电阻部件上,其中第一对电阻部件被适配 以产生差分信号电流,其中所述控制反馈环路适于确保所述差分信号电流进入第二对电阻分量以产生电压输出。 优选地,第一和第二对电阻分量的比率以在第一级的输出处产生具有一些增益的信号的精确副本。

    LOW NOISE, LOW POWER, HIGH LINEARITY DIFFERENTIAL AMPLIFIER WITH A CAPACITIVE INPUT IMPEDANCE
    7.
    发明申请
    LOW NOISE, LOW POWER, HIGH LINEARITY DIFFERENTIAL AMPLIFIER WITH A CAPACITIVE INPUT IMPEDANCE 有权
    低噪声,低功耗,具有电容输入阻抗的高线性差分放大器

    公开(公告)号:US20090045876A1

    公开(公告)日:2009-02-19

    申请号:US11837638

    申请日:2007-08-13

    IPC分类号: H03F3/45

    摘要: A low noise, low power differential two-stage amplifier includes a first stage comprising a pair of electrical devices that sense an input signal difference across the pair of electrical devices; and a control feedback loop operatively connected to the first stage, wherein the first stage in combination with the control loop feedback is adapted to place an exact copy of the signal across a first pair of resistive components, wherein the first pair of resistive components are adapted to generate a differential signal current, wherein the control feedback loop is adapted to ensure that the differential signal current goes a second pair of resistive components to generate a voltage output. Preferably, the first and second pair of resistive components are in ratio to produce the exact copy of the signal with some gain at an output of the first stage.

    摘要翻译: 低噪声,低功率差分两级放大器包括:第一级,包括一对感测一对电气装置上的输入信号差的电气装置; 以及可操作地连接到第一级的控制反馈回路,其中结合控制回路反馈的第一级适合于将信号的精确副本放置在第一对电阻部件上,其中第一对电阻部件被适配 以产生差分信号电流,其中所述控制反馈环路适于确保所述差分信号电流进入第二对电阻分量以产生电压输出。 优选地,第一和第二对电阻分量的比率以在第一级的输出处产生具有一些增益的信号的精确副本。

    Training method and system for collimator border detection method

    公开(公告)号:US11751833B2

    公开(公告)日:2023-09-12

    申请号:US16982709

    申请日:2019-03-22

    IPC分类号: A61B6/00 G06T7/00 G21K1/02

    摘要: A training method (10) and system for a collimator border detection method. The training method (10) comprises the following steps: obtaining an original image acquired by an X-ray imaging system and a processed image obtained after processing the original image (11); determining on the basis of the processed image whether the processed image is a valid image (12); and extracting coordinates of a collimator border of a valid processed image, putting into a training pool the extracted coordinates of the collimator border and the original image corresponding to the valid processed image, and when the number of valid original images in the training pool reaches a preset threshold value, starting the training of the collimator border detection method (13).

    High Voltage Electrostatic Discharge Clamp Using Deep Submicron CMOS Technology
    9.
    发明申请
    High Voltage Electrostatic Discharge Clamp Using Deep Submicron CMOS Technology 有权
    使用深亚微米CMOS技术的高压静电放电钳

    公开(公告)号:US20130215540A1

    公开(公告)日:2013-08-22

    申请号:US13398638

    申请日:2012-02-16

    申请人: Dejun Wang

    发明人: Dejun Wang

    IPC分类号: H02H9/04

    CPC分类号: H01L27/0285 H02H9/046

    摘要: An ESD circuit includes a plurality of MOS devices arranged in a stack, wherein each of the MOS devices comprises a source, a drain, and a gate; a voltage source inputting a supply voltage to the stack of MOS devices; a first plurality of resistors dividing the supply voltage to each source and each drain of the MOS devices in the stack; a second plurality of resistors biasing the supply voltage to each gate of the MOS devices in the stack; an inverter device operatively connected to the second plurality of resistors; a time lag circuit that turns the inverter device on and off; and a plurality of capacitors pulling the voltage to each gate of the MOS devices in the stack to the supply voltage upon the inverter device turning off.

    摘要翻译: ESD电路包括布置在堆叠中的多个MOS器件,其中每个MOS器件包括源极,漏极和栅极; 电压源,向MOS器件堆叠输入电源电压; 第一多个电阻器,用于将电源电压划分为堆叠中的MOS器件的每个源极和每个漏极; 第二多个电阻器,用于将电源电压偏置到堆叠中的MOS器件的每个栅极; 可操作地连接到第二多个电阻器的逆变器装置; 一个使逆变器装置打开和关闭的时滞电路; 以及多个电容器,其将逆变器装置关闭时将堆叠中的MOS器件的各栅极的电压拉至电源电压。

    Multi-Phase Voltage Controlled Oscillator Using Capacitance Degenerated Single Ended Transconductance Stage and Inductance/Capacitance Load
    10.
    发明申请
    Multi-Phase Voltage Controlled Oscillator Using Capacitance Degenerated Single Ended Transconductance Stage and Inductance/Capacitance Load 有权
    使用电容退化单端跨导级和电感/电容负载的多相电压控制振荡器

    公开(公告)号:US20130099871A1

    公开(公告)日:2013-04-25

    申请号:US13276477

    申请日:2011-10-19

    申请人: Dejun Wang

    发明人: Dejun Wang

    IPC分类号: H03K3/03

    CPC分类号: H03K3/0315

    摘要: An electrical circuit includes a first transistor having a first source, a first drain, and a first gate, whereby the first transistor receives an input voltage through the first gate. An output voltage terminal outputs voltage from the first transistor and is connected to the first drain. A second transistor includes a second source, a second drain, and a second gate, whereby the second transistor receives a bias voltage through the second gate, and wherein the first source is connected to the second drain. A first capacitor is connected to the first source, the second source, and the second drain. An inductor is connected to the first drain. A second capacitor is connected in parallel with the inductor and further connected to the first drain.

    摘要翻译: 电路包括具有第一源极,第一漏极和第一栅极的第一晶体管,由此第一晶体管通过第一栅极接收输入电压。 输出电压端子输出来自第一晶体管的电压并连接到第一漏极。 第二晶体管包括第二源极,第二漏极和第二栅极,由此第二晶体管通过第二栅极接收偏置电压,并且其中第一源极连接到第二漏极。 第一电容器连接到第一源极,第二源极和第二漏极。 电感器连接到第一漏极。 第二电容器与电感器并联连接并进一步连接到第一漏极。