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    Layout testing method and wafer manufacturing method
    2.
    发明授权
    Layout testing method and wafer manufacturing method 有权
    布局测试方法和晶圆制造方法

    公开(公告)号：US08356271B2

    公开(公告)日：2013-01-15

    申请号：US13050276

    申请日：2011-03-17

    申请人： Daewook Kim ,  Yong Hee Park ,  Ji-Seong Doh

    发明人： Daewook Kim ,  Yong Hee Park ,  Ji-Seong Doh

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A product layout testing method includes testing and correcting one or more patterns of a product layout, detecting and correcting electrical characteristic changes of transistors of the product layout, and testing whether a product characteristic predicted from the product layout is equal to that predicted from a designed circuit view. Weak points with respect to the pattern may be detected and corrected, electrical characteristic changes depending on layout parameters may be detected and corrected, and whether a circuit operation depending on parasitic components is normal may be checked.

    摘要翻译： 产品布局测试方法包括测试和校正产品布局的一个或多个图案，检测和校正产品布局的晶体管的电特性变化，以及测试从产品布局预测的产品特性是否等于从设计 电路图。 可以检测和校正关于图案的弱点，可以检测和校正根据布局参数的电特性变化，以及根据寄生成分的电路操作是否正常。

    Switching device of networks-on-chip system and scheduling method thereof
    3.
    发明申请
    Switching device of networks-on-chip system and scheduling method thereof 有权
    网络片上系统的切换装置及其调度方法

    公开(公告)号：US20060187953A1

    公开(公告)日：2006-08-24

    申请号：US11326327

    申请日：2006-01-06

    申请人： Gerald Sobelman ,  Man-ho Kim ,  Daewook Kim ,  Sang-woo Rhim ,  Eui-seok Kim ,  Beom-hak Lee

    发明人： Gerald Sobelman ,  Man-ho Kim ,  Daewook Kim ,  Sang-woo Rhim ,  Eui-seok Kim ,  Beom-hak Lee

    IPC分类号： H04J3/02

    CPC分类号： H04L12/66 ,  H04J13/0003 ,  H04J13/0048 ,  H04L49/109 ,  H04L49/3045 ,  H04L49/503

    摘要： A switching device of NoC (Networks on Chip) system and a scheduling method thereof. The switching device has a switching part having a plurality of input ports and a plurality of output ports, and a scheduler for setting a transmission route between the input ports and the output ports, determining the length of code based on the number of input ports having the data among the plurality of input ports, and assigning a predetermined code of the determined code length to the input port and the output port corresponding to the set transmission route. Because the code length is adjustably varied according to the number of transmission packets, switch performance improves.

    摘要翻译： NoC（片上网络）系统的切换装置及其调度方法。 开关装置具有具有多个输入端口和多个输出端口的开关部件，以及用于设定输入端口和输出端口之间的传输路径的调度器，基于具有 多个输入端口之间的数据，并且将所确定的代码长度的预定代码分配给与所设置的传输路由对应的输入端口和输出端口。 由于代码长度可根据传输数据包的数量进行调整，切换性能提高。

    Switching device of networks-on-chip system and scheduling method thereof
    5.
    发明授权
    Switching device of networks-on-chip system and scheduling method thereof 有权
    网络片上系统的切换装置及其调度方法

    公开(公告)号：US07697563B2

    公开(公告)日：2010-04-13

    申请号：US11326327

    申请日：2006-01-06

    申请人： Gerald E. Sobelman ,  Man-ho Kim ,  Daewook Kim ,  Sang-woo Rhim ,  Eui-seok Kim ,  Beom-hak Lee

    发明人： Gerald E. Sobelman ,  Man-ho Kim ,  Daewook Kim ,  Sang-woo Rhim ,  Eui-seok Kim ,  Beom-hak Lee

    IPC分类号： H04J3/02

    CPC分类号： H04L12/66 ,  H04J13/0003 ,  H04J13/0048 ,  H04L49/109 ,  H04L49/3045 ,  H04L49/503

    摘要： A switching device of NoC (Networks on Chip) system and a scheduling method thereof. The switching device has a switching part having a plurality of input ports and a plurality of output ports, and a scheduler for setting a transmission route between the input ports and the output ports, determining the length of code based on the number of input ports having the data among the plurality of input ports, and assigning a predetermined code of the determined code length to the input port and the output port corresponding to the set transmission route. Because the code length is adjustably varied according to the number of transmission packets, switch performance improves.

    摘要翻译： NoC（片上网络）系统的切换装置及其调度方法。 开关装置具有具有多个输入端口和多个输出端口的开关部件，以及用于设定输入端口和输出端口之间的传输路径的调度器，基于具有 多个输入端口之间的数据，并且将所确定的代码长度的预定代码分配给与所设置的传输路由对应的输入端口和输出端口。 由于代码长度可根据传输数据包的数量进行调整，切换性能提高。

    Layout Testing Method and Wafer Manufacturing Method
    6.
    发明申请
    Layout Testing Method and Wafer Manufacturing Method 有权
    布局测试方法和晶圆制造方法

    公开(公告)号：US20110237005A1

    公开(公告)日：2011-09-29

    申请号：US13050276

    申请日：2011-03-17

    申请人： Daewook Kim ,  Yong Hee Park ,  Ji-Seong Doh

    发明人： Daewook Kim ,  Yong Hee Park ,  Ji-Seong Doh

    IPC分类号： H01L21/66 ,  G06F17/50

    CPC分类号： G06F17/5081 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A product layout testing method includes testing and correcting one or more patterns of a product layout, detecting and correcting electrical characteristic changes of transistors of the product layout, and testing whether a product characteristic predicted from the product layout is equal to that predicted from a designed circuit view. Weak points with respect to the pattern may be detected and corrected, electrical characteristic changes depending on layout parameters may be detected and corrected, and whether a circuit operation depending on parasitic components is normal may be checked.

    摘要翻译： 产品布局测试方法包括测试和校正产品布局的一个或多个图案，检测和校正产品布局的晶体管的电特性变化，以及测试从产品布局预测的产品特性是否等于从设计 电路图。 可以检测和校正关于图案的弱点，可以检测和校正根据布局参数的电特性变化，以及根据寄生成分的电路操作是否正常。