公开(公告)号：US07020768B2

公开(公告)日：2006-03-28

申请号：US09792643

申请日：2001-02-26

申请人： Andrew Brookfield Swaine ,  Conrado Blasco Allué ,  Ian Victor Devereux ,  David James Williamson ,  Anthony Neil Berent

发明人： Andrew Brookfield Swaine ,  Conrado Blasco Allué ,  Ian Victor Devereux ,  David James Williamson ,  Anthony Neil Berent

IPC分类号： G06F9/44 ,  G06F11/36

CPC分类号： G06F9/3824 ,  G06F9/3802 ,  G06F11/3466 ,  G06F11/3636

摘要： The present invention provides an apparatus and method for facilitating debugging of sequences of processing instructions. The apparatus comprises a processing circuit for executing processing instructions, the processing circuit having multiple states of operation, with each state of operation being assigned a context identifier to identify the state of operation. Further, logic is provided for facilitating debugging of sequences of processing instructions executed by the processing circuit. The logic comprises control logic, responsive to control parameters, to perform predetermined actions to facilitate debugging, and triggering logic for generating the control parameters dependent on data received from the processing circuit indicative of the processing being performed by the processing circuit. The triggering logic comprises at least one context identifier comparator for comparing a context identifier provided within the data received from the processing circuit with a predetermined context identifier, and to generate a signal indicating whether that context identifier matches the predetermined context identifier. By this approach, the present invention enables a data processing apparatus to be provided with tracing mechanisms and/or debugging mechanisms which can reliably operate even in situations where the sequences of processing instructions from different states of operation occupy overlapping regions in the memory's address space.

摘要翻译： 本发明提供了一种便于调试处理指令序列的装置和方法。 该装置包括用于执行处理指令的处理电路，该处理电路具有多个操作状态，每个操作状态被分配上下文标识符以识别操作状态。 此外，提供逻辑以便于调试由处理电路执行的处理指令的序列。 逻辑包括响应于控制参数的控制逻辑，以执行预定的动作以便于调试，以及触发用于根据从处理电路接收的指示由处理电路执行的处理的数据产生控制参数的逻辑。 触发逻辑包括至少一个上下文标识符比较器，用于将从处理电路接收的数据中提供的上下文标识符与预定上下文标识符进行比较，并产生指示该上下文标识符是否匹配预定上下文标识符的信号。 通过这种方法，本发明使数据处理装置能够提供跟踪机制和/或调试机制，即使在来自不同操作状态的处理指令的序列占据存储器地址空间中的重叠区域的情况下也可以可靠地运行。

公开(公告)号：US08051275B2

公开(公告)日：2011-11-01

申请号：US12457124

申请日：2009-06-01

申请人： David James Williamson ,  Conrado Blasco Allué

发明人： David James Williamson ,  Conrado Blasco Allué

IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F15/00

CPC分类号： G06F9/3836 ,  G06F9/3828

摘要： A processor 2 includes an execution cluster 10 having multiple execution units 14, 16, 18, 20. The execution units 14, 16, 18, 20 share result buses 22, 24. Issue circuitry 12 within the execution cluster 10 determines future availability of a result bus 22, 24 for an instruction to be issued (or recently issued) using a known cycle count for that instruction. The availability is tracked for each result bus using a mask register 32 storing a mask value within which each bit position indicates the availability or non-availability of that result bus at a particular processing cycle in the future. The mask value is left shifted each processing cycle.

摘要翻译： 处理器2包括具有多个执行单元14,16,18,20的执行群集10.执行单元14,16,18,20共享结果总线22,24。执行群集10内的发行电路12确定未来的可用性 结果总线22,24用于使用该指令的已知周期计数来发出（或最近发布）的指令。 使用存储掩码值的掩码寄存器32跟踪每个结果总线的可用性，其中每个位位置指示将来在特定处理周期的该结果总线的可用性或不可用性。 掩码值在每个处理周期左移。

公开(公告)号：US06691270B2

公开(公告)日：2004-02-10

申请号：US09741897

申请日：2000-12-22

申请人： Conrado Blasco Allué ,  Ian Victor Devereux

发明人： Conrado Blasco Allué ,  Ian Victor Devereux

IPC分类号： G01R3128

CPC分类号： G01R31/318558 ,  G01R31/318555

摘要： The present invention provides a technique for operating an integrated circuit comprising a plurality of circuit elements, with a plurality of serial test scan chains, each being coupled to a different one of the circuit elements. A scan chain selector is responsive to a specified scan chain specifying value to select a corresponding one of the plurality of test scan chains. A scan chain controller is also provided which has a serial interface for receiving signals from outside of the integrated circuit, the scan chain controller comprising an instruction decoder for decoding scan chain controller instructions received from the serial interface. In accordance with the present invention, the decoder is responsive to a first scan chain controller instruction to specify a pre-determined scan chain specifying value and a second scan chain controller instruction for decoding by the decoder. The provision of such a first scan chain controller instruction enables the efficiency of the testing procedure to be improved.

摘要翻译： 本发明提供了一种用于操作包括多个电路元件的集成电路的技术，具有多个串行测试扫描链，每个连接测试扫描链均耦合到不同的电路元件。 扫描链选择器响应于指定的扫描链指定值来选择多个测试扫描链中相应的一个。 还提供了一种扫描链控制器，其具有用于从集成电路外部接收信号的串行接口，扫描链控制器包括用于解码从串行接口接收的扫描链控制器指令的指令解码器。 根据本发明，解码器响应于第一扫描链控制器指令来指定预定的扫描链指定值，以及第二扫描链控制器指令以由解码器解码。 提供这种第一扫描链控制器指令使得能够提高测试过程的效率。