公开(公告)号：US08735994B2

公开(公告)日：2014-05-27

申请号：US13431072

申请日：2012-03-27

Applicant: Chia-Chu Liu ,  Kuei Shun Chen ,  Chiang Mu-Chi

Inventor： Chia-Chu Liu ,  Kuei Shun Chen ,  Chiang Mu-Chi

IPC: H01L27/088

CPC classification number: H01L21/28123 ,  H01L29/42372 ,  H01L29/78

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes an electrical-free dummy gate formed over a substrate. The dummy gate has an elongate shape and is oriented along a first direction. The semiconductor device includes a first functional gate formed over the substrate. The first functional gate has an elongate shape and is oriented along the first direction. The first functional gate is separated from the dummy gate in a second direction perpendicular to the first direction. A first conductive contact is formed on the first functional gate. The semiconductor device includes a second functional gate formed over the substrate. The second functional gate has an elongate shape and is oriented along the first direction. The second functional gate is aligned with and physically separated from the dummy gate in the first direction. A second conductive contact is formed on the second functional gate.

Abstract translation: 本发明提供一种半导体器件。 半导体器件包括形成在衬底上的无电虚拟栅极。 虚拟门具有细长形状并且沿着第一方向定向。 半导体器件包括形成在衬底上的第一功能栅极。 第一功能门具有细长形状并且沿着第一方向定向。 第一功能门在垂直于第一方向的第二方向上与虚拟栅极分离。 在第一功能栅极上形成第一导电接触。 半导体器件包括形成在衬底上的第二功能栅极。 第二功能门具有细长形状并且沿着第一方向定向。 第二功能门与第一方向上的虚拟栅极对准并在物理上分离。 在第二功能栅极上形成第二导电接触。

公开(公告)号：US08703392B2

公开(公告)日：2014-04-22

申请号：US13602445

申请日：2012-09-04

Applicant: Yu-Lun Liu ,  Chia-Chu Liu ,  Kuei-Shun Chen ,  Chung-Ming Wang ,  Ying-Hao Su

Inventor： Yu-Lun Liu ,  Chia-Chu Liu ,  Kuei-Shun Chen ,  Chung-Ming Wang ,  Ying-Hao Su

IPC: G03F7/26 ,  B05B7/00 ,  B05C11/00

CPC classification number: G03F7/322

Abstract: The present disclosure involves a method of fabricating a semiconductor device. The method includes providing a substrate having a material layer formed thereon; depositing a photoresist layer on the material layer, the photoresist layer having a vertical dimension; exposing a region of the photoresist layer to radiation, the exposed region having a horizontal dimension, wherein a first ratio of the vertical dimension to the horizontal dimension exceeds a predetermined ratio; and developing the photoresist layer to remove the exposed region at least in part through applying a developer solution containing a first chemical and a second chemical, wherein: the first chemical is configured to dissolve the exposed region of the photoresist layer through a chemical reaction; the second chemical is configured to enhance flow of the first chemical that comes into contact with the photoresist layer; and an optimized second ratio exists between the first chemical and the second chemical.

Abstract translation: 本公开涉及制造半导体器件的方法。 该方法包括提供其上形成有材料层的基板; 在所述材料层上沉积光致抗蚀剂层，所述光致抗蚀剂层具有垂直尺寸; 将所述光致抗蚀剂层的区域暴露于辐射，所述暴露区域具有水平尺寸，其中所述垂直尺寸与所述水平尺寸的第一比例超过预定比率; 并且通过施加包含第一化学品和第二化学品的显影剂溶液，至少部分地显影所述光致抗蚀剂层以去除所述暴露区域，其中：所述第一化学品被配置为通过化学反应溶解所述光致抗蚀剂层的暴露区域; 第二化学品被配置为增强与光致抗蚀剂层接触的第一化学品的流动; 并且在第一化学品和第二化学品之间存在优化的第二比例。

公开(公告)号：US20140065832A1

公开(公告)日：2014-03-06

申请号：US13602697

申请日：2012-09-04

Applicant: Chi-Wen Hsieh ,  Chi-Kang Chang ,  Chia-Chu Liu ,  Meng-Wei Chen ,  Kuei-Shun Chen

Inventor： Chi-Wen Hsieh ,  Chi-Kang Chang ,  Chia-Chu Liu ,  Meng-Wei Chen ,  Kuei-Shun Chen

IPC: H01L21/308 ,  H01L23/544

CPC classification number: H01L23/544 ,  G03F7/70633 ,  G03F7/70683 ,  H01L27/0883 ,  H01L27/0886 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An overlay mark suitable for use in manufacturing nonplanar circuit devices and a method for forming the overlay mark are disclosed. An exemplary embodiment includes receiving a substrate having an active device region and an overlay region. One or more dielectric layers and a hard mask are formed on the substrate. The hard mask is patterned to form a hard mask layer feature configured to define an overlay mark fin. Spacers are formed on the patterned hard mask layer. The spacers further define the overlay mark fin and an active device fin. The overlay mark fin is cut to form a fin line-end used to define a reference location for overlay metrology. The dielectric layers and the substrate are etched to further define the overlay mark fin.

Abstract translation: 公开了适用于制造非平面电路器件的重叠标记和形成覆盖标记的方法。 示例性实施例包括接收具有有源器件区域和覆盖区域的衬底。 在基板上形成一个或多个电介质层和硬掩模。 图案化硬掩模以形成被配置为限定覆盖标记鳍的硬掩模层特征。 间隔物形成在图案化的硬掩模层上。 垫片进一步限定重叠标记鳍片和有源器件鳍片。 覆盖标记鳍被切割以形成用于定义覆盖度量的参考位置的鳍线端。 蚀刻电介质层和衬底以进一步限定覆盖标记鳍。

公开(公告)号：US20130273711A1

公开(公告)日：2013-10-17

申请号：US13449118

申请日：2012-04-17

Applicant: Chia-Chu Liu ,  Kuei-Shun Chen ,  Chih-Hsiung Peng ,  Chi-Kang Chang ,  Chiang Mu-Chi ,  Sheng-Yu Chang ,  Hua Feng Chen ,  Chao-Cheng Chen ,  Ryan Chia-Jen Chen

Inventor： Chia-Chu Liu ,  Kuei-Shun Chen ,  Chih-Hsiung Peng ,  Chi-Kang Chang ,  Chiang Mu-Chi ,  Sheng-Yu Chang ,  Hua Feng Chen ,  Chao-Cheng Chen ,  Ryan Chia-Jen Chen

IPC: H01L21/762

CPC classification number: H01L21/3086 ,  H01L21/76224

Abstract: A method for fabricating a device is disclosed. An exemplary method includes providing a substrate and forming a plurality of fins over the substrate. The method further includes forming a first opening in the substrate in a first longitudinal direction. The method further includes forming a second opening in the substrate in a second longitudinal direction. The first and second longitudinal directions are different. The method further includes depositing a filling material in the first and second openings.

Abstract translation: 公开了一种制造装置的方法。 一种示例性的方法包括提供衬底并在衬底上形成多个鳍。 该方法还包括在第一纵向方向上在基板中形成第一开口。 该方法还包括在第二纵向方向上在基板中形成第二开口。 第一和第二纵向是不同的。 该方法还包括在第一和第二开口中沉积填充材料。

公开(公告)号：US08426810B2

公开(公告)日：2013-04-23

申请号：US13348734

申请日：2012-01-12

Applicant: Bi-Jen Chen ,  Pei-Yi Chen ,  Chiu Chu Liu

Inventor： Bi-Jen Chen ,  Pei-Yi Chen ,  Chiu Chu Liu

IPC: H01J49/00 ,  B01D59/44

CPC classification number: H01L22/12 ,  G01N23/2258 ,  G01N2223/3307 ,  G01N2223/6113

Abstract: A method of planar imaging on semiconductor chips using focused ion beam includes the initial step of disposing at least a positioning symbol to designate a testing area. A metal membrane is positioned on the testing area. The testing chip is trimmed to form a first testing chip. A blind opening is cut proximate to the testing area on the first testing chip forms a second testing chip. The second testing chip is mounted on an inclinable platform. The mounted second testing chip is rotated with the inclinable platform. Ion beams are emitted into the opening at an angle of inclination. Ion beams are emitted in the direction of the incident ray to form planar images of different depths parallel to the metal membrane on the testing area.

Abstract translation: 使用聚焦离子束的半导体芯片上的平面成像方法包括至少设置定位符号以指定测试区域的初始步骤。 金属膜位于测试区域。 测试芯片被修整以形成第一测试芯片。 在第一测试芯片上靠近测试区域切割盲孔形成第二测试芯片。 第二个测试芯片安装在可倾斜的平台上。 安装的第二个测试芯片与可倾斜平台一起旋转。 离子束以倾斜角度发射到开口中。 离子束沿着入射光线的方向发射，以形成与测试区域上的金属膜平行的不同深度的平面图像。

公开(公告)号：US20130095662A1

公开(公告)日：2013-04-18

申请号：US13276168

申请日：2011-10-18

Applicant: Chia-Chu Liu ,  Kuei Shun Chen ,  Meng Wei Chen

Inventor： Chia-Chu Liu ,  Kuei Shun Chen ,  Meng Wei Chen

IPC: H01L21/312 ,  G06F17/50

CPC classification number: H01L21/3086 ,  H01L21/31144 ,  H01L27/0207

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of IC features. The method includes identifying, from the IC design layout, simple features as a first layout wherein the first layout does not violate design rules; and complex features as a second layout wherein the second layout violates the design rules. The method further includes generating a third layout and a fourth layout from the second layout wherein the third layout includes the complex features and connecting features to meet the design rules and the fourth layout includes trimming features.

Abstract translation: 本公开提供了集成电路（IC）设计方法的一个实施例。 该方法包括接收具有多个IC特征的IC设计布局。 该方法包括从IC设计布局识别作为第一布局的简单特征，其中第一布局不违反设计规则; 以及作为第二布局的复杂特征，其中第二布局违反了设计规则。 该方法还包括从第二布局生成第三布局和第四布局，其中第三布局包括复杂特征和连接特征以满足设计规则，并且第四布局包括修剪特征。

公开(公告)号：USD679271S1

公开(公告)日：2013-04-02

申请号：US29419184

申请日：2012-04-25

Applicant: Seung Chu Liu

Designer： Seung Chu Liu

公开(公告)号：US08018091B2

公开(公告)日：2011-09-13

申请号：US12076455

申请日：2008-03-19

Applicant: Huang-Chu Liu ,  Chun-Ta Wu

Inventor： Huang-Chu Liu ,  Chun-Ta Wu

IPC: H02J9/00

CPC classification number: H02J9/061 ,  G06F1/263 ,  Y10T307/50 ,  Y10T307/615 ,  Y10T307/62 ,  Y10T307/625 ,  Y10T307/642 ,  Y10T307/647 ,  Y10T307/653 ,  Y10T307/685 ,  Y10T307/696 ,  Y10T307/724 ,  Y10T307/729

Abstract: A selectable backup power supply device for providing power to a real time clock (RTC) and a memory unit is disclosed. The device includes a backup battery, a first power outputting unit and a second power outputting unit, wherein the backup battery outputs a backup voltage, the first power outputting unit is connected to the backup battery and the RTC for receiving the backup voltage and outputting a first supply voltage to the RTC, and the second power outputting unit is connected to the backup battery and the memory unit, for receiving the backup voltage and, in accordance with a selection signal, outputting a second supply voltage to the memory unit or stopping the output of the second supply voltage.

Abstract translation: 公开了一种用于向实时时钟（RTC）和存储器单元提供电力的可选备用电源装置。 该装置包括备用电池，第一电力输出单元和第二电力输出单元，其中备用电池输出备用电压，第一电力输出单元连接到备用电池和用于接收备用电压的RTC，并输出 向RTC提供第一电源电压，并且第二电力输出单元连接到备用电池和存储单元，用于接收备用电压，并且根据选择信号将第二电源电压输出到存储器单元或停止 输出第二电源电压。

公开(公告)号：US20090236914A1

公开(公告)日：2009-09-24

申请号：US12076455

申请日：2008-03-19

Applicant: Huang-Chu LIU ,  Chun-Ta WU

Inventor： Huang-Chu LIU ,  Chun-Ta WU

IPC: H02J9/00 ,  H02J7/00

CPC classification number: H02J9/061 ,  G06F1/263 ,  Y10T307/50 ,  Y10T307/615 ,  Y10T307/62 ,  Y10T307/625 ,  Y10T307/642 ,  Y10T307/647 ,  Y10T307/653 ,  Y10T307/685 ,  Y10T307/696 ,  Y10T307/724 ,  Y10T307/729

Abstract: A selectable backup power supply device for providing power to a real time clock (RTC) and a memory unit is disclosed. The device includes a backup battery, a first power outputting unit and a second power outputting unit, wherein the backup battery outputs a backup voltage, the first power outputting unit is connected to the backup battery and the RTC for receiving the backup voltage and outputting a first supply voltage to the RTC, and the second power outputting unit is connected to the backup battery and the memory unit, for receiving the backup voltage and, in accordance with a selection signal, outputting a second supply voltage to the memory unit or stopping the output of the second supply voltage.

Abstract translation: 公开了一种用于向实时时钟（RTC）和存储器单元提供电力的可选备用电源装置。 该装置包括备用电池，第一电力输出单元和第二电力输出单元，其中备用电池输出备用电压，第一电力输出单元连接到备用电池和用于接收备用电压的RTC，并输出 向RTC提供第一电源电压，并且第二电力输出单元连接到备用电池和存储单元，用于接收备用电压，并且根据选择信号将第二电源电压输出到存储器单元或停止 输出第二电源电压。

公开(公告)号：US20090223340A1

公开(公告)日：2009-09-10

申请号：US12325108

申请日：2008-11-28

Applicant: Hsuan-Chu LIU ,  Belle Chang

Inventor： Hsuan-Chu LIU ,  Belle Chang

IPC: B27B27/06

CPC classification number: B23D45/14 ,  B23D47/04 ,  Y10T83/6608 ,  Y10T83/6612 ,  Y10T83/762 ,  Y10T83/7697

Abstract: A workpiece feeding device used in a saw machine is disclosed to include a carrier having a base frame movably mounted on the machine base of the saw machine and an angle scale fastened to the base frame, a fence unit having a rip fence pivotally mounted on the base frame of the carrier and biasable relative to the angle scale, a magnetic plate assembly mounted on the base frame of the carrier and carrying a magnetic strip, and a magnetic sensor mounted in the fence unit and movable with the fence unit to measure the biasing angle of the fence unit relative to the angle scale subject to change of magnetic induction between the magnetic sensor and the magnetic strip.

Abstract translation: 公开了一种用于锯床的工件进给装置，包括一个托架，该托架具有可移动地安装在锯床的机器底座上的基架和一个固定在基架上的角尺，一个围栏单元， 载体的基架和相对于角度标尺可偏置的磁性板组件，安装在载体的基架上并承载磁条的磁性板组件和安装在挡板单元中并与挡板单元一起移动以测量偏置的磁传感器 防护罩单元相对于角度尺的角度受到磁传感器和磁条之间磁感应的变化的影响。