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    Process for forming mullite
    1.
    发明授权
    Process for forming mullite 失效
    形成莫来石的方法

    公开(公告)号：US4272500A

    公开(公告)日：1981-06-09

    申请号：US91868

    申请日：1979-11-06

    Applicant: Carl L. Eggerding ,  Frank Gonzales, Jr. ,  Jerzy B. Niklewski

    Inventor： Carl L. Eggerding ,  Frank Gonzales, Jr. ,  Jerzy B. Niklewski

    IPC: C04B35/111 ,  C04B35/18 ,  H05K1/03 ,  C04B35/64

    CPC classification number: C04B35/111 ,  C04B35/18 ,  H05K1/0306

    Abstract: A method of forming ceramic material which includes mullite (3Al.sub.2 O.sub.3.2SiO.sub.2) in any desired percentage. A particulate mixture is formed of (1) mullite in an amount of at least 5% by weight, (2) Al.sub.2 O.sub.3 in an amount to provide sufficient SiO.sub.2 to combine with Al.sub.2 O.sub.3 to form the desired mullite. The mixture is sintered to a temperature in the range of 1300.degree. C. to 1600.degree. C. wherein the Al.sub.2 O.sub.3 and SiO.sub.2 react to form mullite under the influence of the initially added mullite.

    Abstract translation: 一种形成陶瓷材料的方法，其包括任意所需百分比的莫来石（3Al2O3.2SiO2）。 颗粒状混合物由（1）至少5重量％的莫来石形成，（2）Al 2 O 3，其量足以提供足够的SiO 2以与Al 2 O 3结合以形成所需的莫来石。 将混合物烧结至1300℃至1600℃的温度，其中Al 2 O 3和SiO 2在最初加入的莫来石的影响下反应形成莫来石。

    Window via capacitors
    2.
    发明授权
    Window via capacitors 有权
    通过电容窗

    公开(公告)号：US07573698B2

    公开(公告)日：2009-08-11

    申请号：US11517536

    申请日：2006-09-07

    Applicant: Carl L. Eggerding ,  Jason MacNeal ,  John L. Galvagni ,  Andrew P. Ritter

    Inventor： Carl L. Eggerding ,  Jason MacNeal ,  John L. Galvagni ,  Andrew P. Ritter

    IPC: H01G4/228 ,  H01G4/06

    CPC classification number: H01G4/30 ,  H01G4/12 ,  H01G4/232

    Abstract: A method of forming a window via capacitor comprises a first step of providing a plurality of interleaved dielectric layers and paired electrode layers to create a multilayered arrangement characterized by top and bottom surfaces and a plurality pf side surfaces. First and second transition layer electrode portions are provided on a top surface of the multilayered arrangement on top of which a cover layer formed to define openings, or windows, therein is provided. The cover layer may be provided before device firing or may be printed on after firing using polymer or glass. Peripheral terminations are subsequently formed on the device periphery to connect selected electrode layers to respective transition layer electrode portions. Via terminations are formed in the cover layer openings, on top of which solder balls may be applied. Some of the terminations may be formed in accordance with various plating techniques as disclosed.

    Abstract translation: 一种通过电容器形成窗户的方法包括提供多个交错电介质层和成对电极层的第一步骤，以产生以顶表面和底表面以及多个侧表面为特征的多层布置。 第一过渡层电极部分和第二过渡层电极部分设置在多层结构的顶表面上，其上形成有限定开口或其中的窗口的覆盖层。 覆盖层可以在器件烧制之前提供，或者可以在使用聚合物或玻璃烧制后印刷。 随后在器件外围形成外围端子，以将所选择的电极层连接到各自的过渡层电极部分。 通孔端子形成在覆盖层开口中，其上可以施加焊球。 一些终端可以根据所公开的各种电镀技术形成。

    Anode for use in electrolytic capacitors
    3.
    发明申请
    Anode for use in electrolytic capacitors 审中-公开
    阳极用于电解电容器

    公开(公告)号：US20080232032A1

    公开(公告)日：2008-09-25

    申请号：US11725983

    申请日：2007-03-20

    Applicant: Brady Jones ,  Carl L. Eggerding ,  Allen Butler ,  Gang Ning ,  Kaye Poole ,  Craig William Nies

    Inventor： Brady Jones ,  Carl L. Eggerding ,  Allen Butler ,  Gang Ning ,  Kaye Poole ,  Craig William Nies

    IPC: H01G9/042 ,  H01G9/145 ,  H01R43/16

    CPC classification number: H01G9/052 ,  H01G9/0032 ,  Y10T29/49204

    Abstract: A capacitor anode that is formed from ceramic particles (e.g., Nb2O5, Ta2O5) capable of being chemically reduced to form an electrically conductive composition (e.g., NbO, Ta) is provided. For instance, a slip composition containing the ceramic particles may be initially formed and deposited onto a carrier substrate in the form of a thin layer. If desired, multiple layers may be formed to achieve the target thickness for the anode. Once formed, the layer(s) are subjected to a heat treatment to chemically reduce the ceramic particles and form the electrically conductive anode. Contrary to conventional press-formed anodes, the slip-formed anodes of the present invention may exhibit a small thickness, high aspect ratio (i.e., ratio of width to thickness), and uniform density, which may in turn may lead to an improved volumetric efficiency and equivalent series resistance (“ESR”).

    Abstract translation: 由陶瓷颗粒（例如Nb 2 O 5，Ta 2 O 5）形成的电容器阳极， 能够被化学还原以形成导电组合物（例如，NbO，Ta）。 例如，可以初始形成含有陶瓷颗粒的滑动组合物，并以薄层的形式沉积到载体基材上。 如果需要，可以形成多个层以实现阳极的目标厚度。 一旦形成，就对该层进行热处理以化学还原陶瓷颗粒并形成导电阳极。 与传统的压制成型阳极相反，本发明的形成滑动的阳极可以表现出小的厚度，高纵横比（即，宽度与厚度之比）和均匀的密度，这又可能导致改进的体积 效率和等效串联电阻（“ESR”）。

    Land grid feedthrough low ESL technology
    4.
    发明授权
    Land grid feedthrough low ESL technology 有权
    土地电网馈通低ESL技术

    公开(公告)号：US08238116B2

    公开(公告)日：2012-08-07

    申请号：US12061150

    申请日：2008-04-02

    Applicant: Carl L. Eggerding ,  Andrew P. Ritter

    Inventor： Carl L. Eggerding ,  Andrew P. Ritter

    IPC: H05K1/14 ,  H05K1/11

    CPC classification number: H05K1/0231 ,  H01G4/012 ,  H01G4/232 ,  H01G4/30 ,  H01G4/35 ,  H05K1/113 ,  H05K2201/0792 ,  H05K2201/09309 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/435 ,  Y10T29/4913

    Abstract: Disclosed are apparatus and methodology for providing land grid feedthrough capacitor designs having broad applicability to signal and power filtering technologies. Such capacitor designs provide characteristics for use in decoupling applications involving both signal level and power level environments. Low equivalent series inductance (ESL) is provided by current cancellation techniques involving opposite current flow in power or signal and ground current paths through the device.

    Abstract translation: 公开了用于提供具有广泛适用于信号和功率滤波技术的陆地电网馈通电容器设计的装置和方法。 这种电容器设计提供了用于涉及信号电平和功率级环境的去耦应用的特性。 低等效串联电感（ESL）由电流消除技术提供，包括通过器件的电源或信号和接地电流路径中的相反电流。

    Dielectric substrates comprising cordierite and method of forming the same
    6.
    发明授权
    Dielectric substrates comprising cordierite and method of forming the same 失效
    包含堇青石的介电基材及其形成方法

    公开(公告)号：US4540621A

    公开(公告)日：1985-09-10

    申请号：US518588

    申请日：1983-07-29

    Applicant: Carl L. Eggerding ,  Edward A. Giess

    Inventor： Carl L. Eggerding ,  Edward A. Giess

    IPC: C04B35/195 ,  C04B35/634 ,  H01L21/48 ,  H01L23/15 ,  H05K1/03 ,  H05K3/46 ,  H05K3/30 ,  H05K3/00

    CPC classification number: C04B35/63416 ,  C04B35/195 ,  C04B35/634 ,  C04B35/6342 ,  H01L21/4807 ,  H01L23/15 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  Y10T428/24917

    Abstract: A method for forming a substrate for electronic applications having a dielectric constant of less than 6 is disclosed. The method comprises admixing crystalline cordierite particles having a size of 0.1--10 microns with a binder and solvent, casting the same into a sheet, drying the cast sheet into a self-supporting green sheet and then heating the green sheet to burn out the binder and to sinter the particles together. A metallization pattern is deposited on the green sheet after the casting but before the heating, the metallization pattern being molybdenum or tungsten. The cordierite has a defined coefficient of thermal expansion. A dielectric substrate for mounting of integrated circuit devices thereon is also disclosed.

    Abstract translation: 公开了一种形成介电常数小于6的电子应用基板的方法。 该方法包括将具有0.1-10微米尺寸的结晶堇青石颗粒与粘合剂和溶剂混合，将其浇注到片材中，将流延片材干燥成自支撑生片，然后加热生片以烧尽粘合剂 并将颗粒烧结在一起。 金属化图案在铸造之后但在加热之前沉积在生片上，金属化图案是钼或钨。 堇青石具有确定的热膨胀系数。 还公开了用于在其上安装集成电路器件的电介质基片。

    Multilayer vertically integrated array technology
    7.
    发明授权
    Multilayer vertically integrated array technology 有权
    多层垂直集成阵列技术

    公开(公告)号：US07724496B2

    公开(公告)日：2010-05-25

    申请号：US11590681

    申请日：2006-10-31

    Applicant: Carl L. Eggerding ,  Ronald S. Demcko ,  John L. Galvagni

    Inventor： Carl L. Eggerding ,  Ronald S. Demcko ,  John L. Galvagni

    IPC: H01G4/005 ,  H01G4/228

    CPC classification number: H01G4/40 ,  H01C1/142 ,  H01C1/148 ,  H01C7/18 ,  H01G4/012 ,  H01G4/30 ,  H01G4/35

    Abstract: The present subject matter is directed to methods and apparatus for providing a multilayer array component with interdigitated electrode layer portions configured to selectively provide signal filtering characteristics, over-voltage transient suppression capabilities, and land grid array (LGA) terminations. Embodiments of the present subject matter may define a single capacitor, a capacitor array, or a multilayer vertically integrated array with configurable equivalent electrical characteristics including equivalent series inductance (ESL), equivalent series resistance (ESR), and configurable capacitance and voltage clamping and transient suppression capabilities.

    Abstract translation: 本发明涉及用于提供具有交错电极层部分的多层阵列部件的方法和装置，其配置为选择性地提供信号滤波特性，过电压瞬变抑制能力和平面栅格阵列（LGA）终端。 本主题的实施例可以定义单个电容器，电容器阵列或具有可配置的等效电特性的多层垂直集成阵列，包括等效串联电感（ESL），等效串联电阻（ESR）以及可配置的电容和电压钳位和瞬态 抑制能力。

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