公开(公告)号：US08321779B2

公开(公告)日：2012-11-27

申请号：US12215726

申请日：2008-06-30

Applicant: Beom-Ju Shin ,  Sang-Sic Yoon

Inventor： Beom-Ju Shin ,  Sang-Sic Yoon

IPC: G06F11/10 ,  G06F11/30

CPC classification number: H03M13/091 ,  G06F11/1004

Abstract: Semiconductor device includes a pad for outputting a cyclic redundancy check (CRC) data for error detection and a signal outputting unit for outputting the CRC data or a data strobe signal, which is output together with data of being output in response to a read command, through the pad according to operation modes. Method for operating a semiconductor device provided a step of outputting a CRC data for error detection through a CRC data pad and a step of outputting a data strobe signal, which is output together with data output in response to a read command, through the CRC data pad according to an operation mode.

Abstract translation: 半导体器件包括用于输出用于错误检测的循环冗余校验（CRC）数据的焊盘和用于输出CRC数据或数据选通信号的信号输出单元，该数据选通信号与响应于读命令而被输出的数据一起输出， 根据操作模式通过垫。 用于操作半导体器件的方法提供了通过CRC数据焊盘输出用于错误检测的CRC数据的步骤，以及输出与响应于读取命令输出的数据一起通过CRC数据输出的数据选通信号的步骤 按照操作模式进行操作。

公开(公告)号：US08243543B2

公开(公告)日：2012-08-14

申请号：US12217019

申请日：2008-06-30

Applicant: Beom-Ju Shin ,  Sang-Sic Yoon

Inventor： Beom-Ju Shin ,  Sang-Sic Yoon

IPC: G11C7/00

CPC classification number: G11C7/1018 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1078 ,  G11C2207/107

Abstract: Semiconductor memory device for high-speed data input/output includes a first serializer configured to partially serialize input 8-bit parallel data to output first to fourth serial data, a second serializer configured to partially serialize the first to fourth serial data to output fifth and sixth serial data and a third serializer configured to serialize the fifth and sixth serial data to output seventh serial data.

Abstract translation: 用于高速数据输入/输出的半导体存储器件包括：第一串行器，被配置为部分地串行输入8位并行数据以输出第一至第四串行数据;第二串行器，被配置为部分串行化第一至第四串行数据以输出第五和第五串行数据; 第六串行数据和第三串行器，被配置为串行化第五和第六串行数据以输出第七串行数据。

公开(公告)号：US08050110B2

公开(公告)日：2011-11-01

申请号：US12640883

申请日：2009-12-17

Applicant: Sang-Jin Byeon ,  Beom-Ju Shin

Inventor： Sang-Jin Byeon ,  Beom-Ju Shin

IPC: G11C7/10

CPC classification number: G11C7/1048

Abstract: A semiconductor memory device of the claimed invention, having an active state for performing a read or write operation and an inactive state except for the active state includes a data input/output (I/O) line; a pull-up latch unit for pulling-up the data I/O line when the semiconductor memory device is in the inactive state; a pull-down latch unit for pulling-down the data I/O line when the semiconductor memory device is in the inactive state; and a selection unit for selectively driving one of the pull-up latch unit and the pull-down latch unit.

Abstract translation: 具有用于执行读或写操作的活动状态和除活动状态之外的非活动状态的所要求保护的发明的半导体存储器件包括数据输入/输出（I / O）线; 上拉锁存单元，用于在半导体存储器件处于非活动状态时拉起数据I / O线; 一个下拉锁存单元，用于在半导体存储器件处于非活动状态时下拉数据I / O线; 以及选择单元，用于选择性地驱动上拉锁存单元和下拉锁存单元中的一个。

公开(公告)号：US08010586B2

公开(公告)日：2011-08-30

申请号：US11878091

申请日：2007-07-20

Applicant: Beom-Ju Shin

Inventor： Beom-Ju Shin

IPC: G06F15/00

CPC classification number: H03K19/0016

Abstract: An apparatus for generating a DBI signal in a semiconductor integrated circuit includes a full adder that includes data input terminals and a carry input terminal, each of which receives data, performs an operation on the received data, thereby outputting a sum and a carry. A half adder includes data input terminals, each of which receives data, performs an operation on the received data, thereby outputting a sum and a carry. A DBI determining unit determines a logic value of each of the data according to the sums and the carries that are transmitted from the full adder and the half adder, thereby outputting a DBI signal.

Abstract translation: 一种用于在半导体集成电路中产生DBI信号的装置包括：全加器，包括数据输入端和进位输入端，每个输入端接收数据，对所接收的数据进行操作，从而输出和和进位。 半加法器包括数据输入端，每个数据输入端接收数据，对接收到的数据执行操作，从而输出和和进位。 DBI确定单元根据从全加器和半加法器发送的总和和运算来确定每个数据的逻辑值，从而输出DBI信号。

公开(公告)号：US07994833B2

公开(公告)日：2011-08-09

申请号：US12631611

申请日：2009-12-04

Applicant: Beom-Ju Shin

Inventor： Beom-Ju Shin

IPC: H03L7/06

CPC classification number: H03L7/0814

Abstract: A semiconductor device comprises a delay locked loop (DLL) configured to control a phase delay of an internal clock to output first and second DLL clocks; an output enable unit configured to generate rising/falling data output enable signals in response to the second DLL clocks; and an output driver configured to output data in response to one of the first DLL clocks selected by the rising/falling data output enable signals, where a phase of the second DLL clock leads that of the first DLL clock.

Abstract translation: 半导体器件包括被配置为控制内部时钟的相位延迟以输出第一和第二DLL时钟的延迟锁定环（DLL）; 输出使能单元，被配置为响应于所述第二DLL时钟产生上升/下降数据输出使能信号; 以及输出驱动器，其被配置为响应于由所述上升/下降数据输出使能信号选择的所述第一DLL时钟之一来输出数据，其中所述第二DLL时钟的相位引导所述第一DLL时钟的相位。

公开(公告)号：US20100287337A1

公开(公告)日：2010-11-11

申请号：US12700400

申请日：2010-02-04

Applicant: Beom Ju Shin ,  Kyoung Nam Kim

Inventor： Beom Ju Shin ,  Kyoung Nam Kim

IPC: G06F12/00 ,  G06F1/04

CPC classification number: G11C16/20 ,  G11C15/00 ,  G11C16/10

Abstract: A nonvolatile memory device has a memory cell array including a memory cell group for storing option information, and a controller configured to wait for a preset period of time after a command for loading the option information has been received before performing an operation of loading the option information.

Abstract translation: 非易失性存储器件具有包括用于存储选项信息的存储单元组的存储单元阵列，以及控制器，被配置为在执行加载选项的操作之前，在接收到用于加载选项信息的命令之后等待预设的时间段 信息。

公开(公告)号：US20100284230A1

公开(公告)日：2010-11-11

申请号：US12701877

申请日：2010-02-08

Applicant: Beom Ju Shin

Inventor： Beom Ju Shin

IPC: G11C7/00

CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/26

Abstract: A method of operating a nonvolatile memory device includes supplying a variable voltage of a first voltage level to a selected page buffer and supplying the variable voltage to a first bit line, coupled to a selected memory cell selected for data reading, for a first time period, cutting off the supply of the variable voltage to the first bit line, after the first time period, and precharging the first bit line to a second voltage level through a sense node of the selected page buffer, which is in a precharge state, evaluating a voltage of the first bit line, after the precharging of the first bit line, so that the voltage of the first bit line is shifted according to a program state of the selected memory cell, and sensing the voltage of the evaluated first bit line and latching data in the selected memory cell.

Abstract translation: 一种操作非易失性存储器件的方法包括：将第一电压电平的可变电压提供给所选择的页面缓冲器，并将可变电压提供给第一位线，该第一位线耦合到第一时间段中被选择用于数据读取的所选存储器单元 在第一时间段之后切断对第一位线的可变电压的供应，并且通过处于预充电状态的所选择的页面缓冲器的感测节点将第一位线预充电到第二电压电平，评估 第一位线的电压在第一位线的预充电之后，使得第一位线的电压根据所选存储单元的编程状态而偏移，并且感测所评估的第一位线的电压，以及 在所选存储单元中锁存数据。

公开(公告)号：US07742349B2

公开(公告)日：2010-06-22

申请号：US12164045

申请日：2008-06-28

Applicant: Chun-Seok Jeong ,  Beom-Ju Shin

Inventor： Chun-Seok Jeong ,  Beom-Ju Shin

IPC: G11C7/00

CPC classification number: G11C29/14 ,  G11C7/1045 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/48

Abstract: A circuit can control a bit rate of information output from a multi-purpose register (MPR) of a semiconductor memory device in a test mode, thereby reducing current consumption for outputting information in a multi-purpose register (MPR). The semiconductor memory device includes a multi-purpose register configured separately to store a plurality of information, and to control a bit rate of the stored information in a test mode, each of the information having multiple bits, and a connection selector configured selectively to connect an output terminal of the multi-purpose register to one of a number of global lines according to an operation mode.

Abstract translation: 电路可以在测试模式中控制从半导体存储器件的多用途寄存器（MPR）输出的信息的比特率，从而减少用于在多用途寄存器（MPR）中输出信息的电流消耗。 半导体存储器件包括分别配置以存储多个信息的多用途寄存器，并且在测试模式下控制所存储的信息的比特率，每个信息具有多个位，以及连接选择器，其被选择性地配置为连接 根据操作模式将多功能寄存器的输出端子连接到多条全局线路之一。

公开(公告)号：US20100073053A1

公开(公告)日：2010-03-25

申请号：US12631611

申请日：2009-12-04

Applicant: Beom-Ju Shin

Inventor： Beom-Ju Shin

IPC: H03L7/06

CPC classification number: H03L7/0814

Abstract: A semiconductor device comprises a delay locked loop (DLL) configured to control a phase delay of an internal clock to output first and second DLL clocks; an output enable unit configured to generate rising/falling data output enable signals in response to the second DLL clocks; and an output driver configured to output data in response to one of the first DLL clocks selected by the rising/falling data output enable signals, where a phase of the second DLL clock leads that of the first DLL clock.

Abstract translation: 半导体器件包括被配置为控制内部时钟的相位延迟以输出第一和第二DLL时钟的延迟锁定环（DLL）; 输出使能单元，被配置为响应于所述第二DLL时钟产生上升/下降数据输出使能信号; 以及输出驱动器，其被配置为响应于由所述上升/下降数据输出使能信号选择的所述第一DLL时钟之一来输出数据，其中所述第二DLL时钟的相位引导所述第一DLL时钟的相位。

公开(公告)号：US20090251187A1

公开(公告)日：2009-10-08

申请号：US12347126

申请日：2008-12-31

Applicant: Beom-Ju SHIN

Inventor： Beom-Ju SHIN

IPC: H03H11/26

CPC classification number: H03H11/26 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222

Abstract: An output enable signal generating circuit including a first count value generation unit that provides a first count value by executing a counting operation, starting from an initial count value corresponding to a CAS latency information, the counting operation being executed in response to an internal clock signal, a second count value generation unit that provides a second count value that is counted in response to an external clock signal and an output enable signal generation unit for generating an output enable signal that is activated at every timing when the second count value and the first count value become equal to each other, in response to each of a plurality of read commands.

Abstract translation: 一种输出使能信号发生电路，包括：第一计数值生成单元，其通过执行计数操作来提供第一计数值，从对应于CAS等待时间信息的初始计数值开始，响应于内部时钟信号执行的计数操作 第二计数值生成单元，其提供响应于外部时钟信号而被计数的第二计数值;以及输出使能信号生成单元，用于产生在第二计数值和第一计数值的每个定时激活的输出使能信号 响应于多个读取命令中的每一个，计数值变得彼此相等。