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9 条记录 (耗时 0.02 秒)

    Phase lock detector
    1.
    发明授权
    Phase lock detector 有权
    锁相检测器

    公开(公告)号：US07480361B1

    公开(公告)日：2009-01-20

    申请号：US10889553

    申请日：2004-07-12

    申请人： Qi Zhang ,  Atul Ghia

    发明人： Qi Zhang ,  Atul Ghia

    IPC分类号： H03D3/24

    CPC分类号： H03L7/095 ,  H03L7/0812

    摘要： Method and apparatus for phase lock detection is described. More particularly, a phase lock detection circuit (20) includes a synchronization circuit (23) coupled to receive a reference signal (31) and configured to provide a derivative signal (32). A phase lock detector (21) is coupled to receive the reference signal (31) and the derivative signal (32) and is configured to provide a cycle lock signal (24) indicating whether a phase lock exists within a lock window (57) for a clock cycle.

    摘要翻译： 描述用于锁相检测的方法和装置。 更具体地，锁相检测电路（20）包括耦合以接收参考信号（31）并被配置为提供导数信号（32）的同步电路（23）。 相位锁定检测器（21）被耦合以接收参考信号（31）和微分信号（32），并且被配置为提供循环锁定信号（24），其指示在锁定窗口（57）内是否存在相位锁定，用于 一个时钟周期。

    Bimodal serial to parallel converter with bitslip controller
    3.
    发明授权
    Bimodal serial to parallel converter with bitslip controller 有权
    双模串行到并行转换器与位滑控制器

    公开(公告)号：US06985096B1

    公开(公告)日：2006-01-10

    申请号：US10919900

    申请日：2004-08-17

    申请人： Paul T. Sasaki ,  Jason R. Bergendahl ,  Atul Ghia ,  Jian Tan

    发明人： Paul T. Sasaki ,  Jason R. Bergendahl ,  Atul Ghia ,  Jian Tan

    IPC分类号： H03M9/00

    CPC分类号： H03M9/00 ,  H03K5/135

    摘要： Method and apparatus for a bimodal serial to parallel converter is provided. A first stage of registers is clocked responsive to a clock signal, such as a forwarded clock signal of a synchronous interface. The first stage of registers is configurable in either a single serial shift chain or two serial shift chains. The former configuration is for Single Data Rate (“SDR”) data, and the latter configuration is for Double Data Rate (“DDR”) data. A bitslip controller is configured to provide a control select signal to selection circuitry. For DDR operation, the control signal is for selecting respective portions of outputs from the two serial shift chains for providing to a second stage of registers. For DDR operation, the second stage of registers is alternatively clocked responsive to a divided down version of the clock signal and another divided down version of the clock signal which is periodically stopped.

    摘要翻译： 提供了一种双模串并转换器的方法和装置。 响应于时钟信号（诸如同步接口的转发时钟信号）对寄存器的第一级进行时钟控制。 寄存器的第一级可以在单个串行移位链或两个串行移位链中进行配置。 前一种配置用于单数据速率（“SDR”）数据，后一种配置用于双倍数据速率（“DDR”）数据。 位位控制器被配置为向选择电路提供控制选择信号。 对于DDR操作，控制信号用于选择来自两个串行移位链的输出的相应部分以提供给第二级寄存器。 对于DDR操作，响应于时钟信号的分频版本和周期性地停止的时钟信号的另一个分频模式，寄存器的第二级可选地进行时钟控制。

    Differential clock tree in an integrated circuit
    6.
    发明申请
    Differential clock tree in an integrated circuit 有权
    差分时钟树在集成电路中

    公开(公告)号：US20070013428A1

    公开(公告)日：2007-01-18

    申请号：US11511779

    申请日：2006-08-29

    申请人： Vasisht Vadi ,  Steven Young ,  Atul Ghia ,  Adebabay Bekele ,  Suresh Menon

    发明人： Vasisht Vadi ,  Steven Young ,  Atul Ghia ,  Adebabay Bekele ,  Suresh Menon

    IPC分类号： G06F1/04

    CPC分类号： G06F1/10 ,  H03K5/2481

    摘要： A clock distribution network having: a main trunk configured to provide a differential clock signal; a plurality of branches coupled to the main trunk for distributing the differential clock signal to a plurality of circuit elements on the integrated circuit; and a plurality of switches coupling the main trunk to the plurality of branches.

    摘要翻译： 一种时钟分配网络，具有：主干线，被配置为提供差分时钟信号; 耦合到所述主干线的多个分支，用于将所述差分时钟信号分配给所述集成电路上的多个电路元件; 以及将主干线连接到多个分支的多个开关。

    Programmable logic device having an embedded differential clock tree
    7.
    发明申请
    Programmable logic device having an embedded differential clock tree 有权
    具有嵌入式差分时钟树的可编程逻辑器件

    公开(公告)号：US20050242866A1

    公开(公告)日：2005-11-03

    申请号：US10837009

    申请日：2004-04-30

    申请人： Vasisht Vadi ,  Steven Young ,  Atul Ghia ,  Adebabay Bekele ,  Suresh Menon

    发明人： Vasisht Vadi ,  Steven Young ,  Atul Ghia ,  Adebabay Bekele ,  Suresh Menon

    IPC分类号： G06F1/10 ,  H03F3/45 ,  H03K5/15 ,  H03K19/177

    CPC分类号： G06F1/10 ,  H03K5/15013 ,  H03K19/1774 ,  H03K19/17784 ,  H03K19/17796

    摘要： A clock distribution network having: a backbone clock signal line configured to provide a differential clock signal; multiple branches coupled to the backbone clock signal line for distributing the differential clock signal to multiple programmable function elements; a first leaf node coupled to a first branch, where the first leaf node is configured to provide the differential clock signal to a first programmable function element; and a second leaf node coupled to a second branch, where the second leaf node is configured to provide a single ended clock signal derived from the differential clock signal to a second programmable function element.

    摘要翻译： 一种时钟分配网络，具有：骨干时钟信号线，被配置为提供差分时钟信号; 多个分支耦合到主干时钟信号线，用于将差分时钟信号分配给多个可编程功能元件; 耦合到第一分支的第一叶节点，其中所述第一叶节点被配置为将所述差分时钟信号提供给第一可编程功能元件; 以及耦合到第二分支的第二叶节点，其中所述第二叶节点被配置为将从所述差分时钟信号导出的单端时钟信号提供给第二可编程功能元件。

    Differential clocking scheme in an integrated circuit having digital multiplexers
    8.
    发明申请
    Differential clocking scheme in an integrated circuit having digital multiplexers 有权
    具有数字多路复用器的集成电路中的差分时钟方案

    公开(公告)号：US20050242867A1

    公开(公告)日：2005-11-03

    申请号：US10837388

    申请日：2004-04-30

    申请人： Atul Ghia ,  Adebabay Bekele

    发明人： Atul Ghia ,  Adebabay Bekele

    IPC分类号： H03K5/22 ,  H03K19/177

    CPC分类号： H03K19/1774 ,  H03K19/17784 ,  H03K19/17792

    摘要： A system for distributing a small signal differential signal to a circuit element. The system includes: a first converter configured to convert a first small signal differential signal to a first two phase full CMOS differential signal for input into the differential multiplexer; and a programmable driver circuit configured to boost an output current of the programmable driver circuit at selected frequencies and to convert two phase full CMOS differential signal outputs of the differential multiplexer to a second small signal differential signal.

    摘要翻译： 一种用于将小信号差分信号分配给电路元件的系统。 该系统包括：第一转换器，其被配置为将第一小信号差分信号转换为第一两相全CMOS差分信号，以输入到差分多路复用器; 以及可编程驱动器电路，其被配置为以选定频率升高可编程驱动器电路的输出电流，并将差分多路复用器的两相全CMOS差分信号输出转换为第二小信号差分信号。