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    Multiprocessor communications register providing complete access in a full access mode, and mapped access in a partial access mode
    1.
    发明授权
    Multiprocessor communications register providing complete access in a full access mode, and mapped access in a partial access mode 失效
    多处理器通信寄存器以完全访问模式提供完整访问，并以部分访问模式进行映射访问

    公开(公告)号：US5261108A

    公开(公告)日：1993-11-09

    申请号：US995907

    申请日：1992-12-22

    Applicant: Hideo Hayashi ,  Atsuo Mochizuki ,  Ryuji Kobayashi ,  Chiaki Kumamoto ,  Reiko Kokubu

    Inventor： Hideo Hayashi ,  Atsuo Mochizuki ,  Ryuji Kobayashi ,  Chiaki Kumamoto ,  Reiko Kokubu

    IPC: G06F9/46 ,  G06F13/362 ,  G06F15/167 ,  G06F13/14 ,  G06F12/06

    CPC classification number: G06F15/167 ,  G06F13/362 ,  G06F9/526 ,  G06F2209/521

    Abstract: In a multiprocessor system, a communication register is partitioned into groups of word storage locations and one of the groups is further partitioned into subgroups associated respectively with the processors. An access controller accesses any groups of the communication register when a system program is being processed and accesses one of the subgroup when a user program is being processed. A write controller is responsive to a test & set instruction of first occurrence from a common bus for assembling a lock work with a data word, a control field and a counter field containing a variable count. The control field of the lock word is set to a first binary state when it is assembled and reset to a second binary state when deassembled. In response to a load instruction from the common bus, either the data word from the bus or lock word is stored into a specified storage area of a communication register. A read controller reads contents of an addressed location of the communication register onto the common bus in response to a save instruction. Test & set instruction of a subsequent occurrence causes the variable count in the stored lock word to be decremented as long as the control field remains set to the first binary state. When the count reduces to zero, a signal is applied to the common bus indicating the occurrence of a dead lock.

    Abstract translation: 在多处理器系统中，通信寄存器被划分成字存储位置的组，并且该组中的一个被进一步划分为分别与处理器相关联的子组。 当正在处理系统程序时，访问控制器访问通信寄存器的任何组，并且当正在处理用户程序时访问该子组中的一个。 写控制器响应于来自公共总线的第一次出现的测试和设置指令，用于组合具有数据字的锁定工作，控制字段和包含可变计数的计数器字段。 当组装时，锁定字的控制字段被设置为第一个二进制状态，并且在重新组装时将其复位到第二个二进制状态。 响应于来自公共总线的加载指令，来自总线或锁定字的数据字被存储到通信寄存器的指定存储区域中。 读取控制器响应于保存指令将通信寄存器的寻址位置的内容读取到公共总线上。 只要控制字段保持设置为第一个二进制状态，随后发生的测试和设置指令会导致存储的锁定字中的变量计数递减。 当计数减少为零时，将信号施加到公共总线，指示发生死锁。

    System for prefetching vector data based on the status of the vector registers
    4.
    发明授权
    System for prefetching vector data based on the status of the vector registers 失效
    基于矢量寄存器的状态预测矢量数据的系统

    公开(公告)号：US5237702A

    公开(公告)日：1993-08-17

    申请号：US419734

    申请日：1989-10-11

    Applicant: Hideo Hayashi ,  Atsuo Mochizuki

    Inventor： Hideo Hayashi ,  Atsuo Mochizuki

    IPC: G06F17/16 ,  G06F9/38 ,  G06F15/78

    CPC classification number: G06F15/8069 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838

    Abstract: In a vector processor, a decoder generates a load request signal if an instruction stored in an instruction register is a vector load instruction and causes the instruction to be transferred to a stack. A resource manager has a plurality of flags associated respectively with vector registers provided in a calculation circuit and constantly updates the flags in accordance with contents of the associated vector registers. A contention detector is responsive to a vector load instruction being loaded into the stack for generating a proceed-to-transfer signal if no contention is detected between the vector load instruction and a corresponding flag in the resource manager. A buffer is provided in a memory controller for storing vector data from the memory in response to the load request signal from the decoder and transferring it to the calculation circuit in response to the proceed-to-transfer signal from the contention detector.

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