公开(公告)号：US10441618B2

公开(公告)日：2019-10-15

申请号：US15770620

申请日：2016-10-21

申请人： Kazuhiko Sugiura ,  Aditya Kulkarni

发明人： Kazuhiko Sugiura ,  Aditya Kulkarni

IPC分类号： A61K36/18 ,  A61K36/185 ,  A23L2/52 ,  A23G3/34 ,  A23G4/00 ,  A23L33/105 ,  A23L9/10 ,  A23F5/46 ,  A23G3/48 ,  A23G4/06 ,  A23G9/42 ,  A23L2/54 ,  A61K31/7034 ,  A23G1/48 ,  A23G3/36 ,  A23L2/39

摘要： A moringa extract containing a benzyl glucosinolate in a content of 6% by mass or more, calculated as a dry solid content of the extract, wherein the extract does not substantially contain an alkaloid. The moringa extract of the present invention for solving a first aspect is useful in the field of foodstuff or the like. Also, the PPAR activator of the present invention for solving a second aspect has excellent PPAR activation action, and has no disadvantages in side effects, so that it can be ingested for long term, which can be preferably used in foodstuff and the like. Therefore, the PPAR activator of the present invention for solving a second aspect can be expected to be used as a food, a supplement or a medicament not only for prevention of disease such as insulin resistance, hyperinsulinism, Type 2 diabetes, hypertension, hyperlipidemia, arterial sclerosis and obesity, but also for fatigue recovery or endurance improvement by improving basal metabolism. In addition, a benzyl glucosinolate-containing composition for solving a third aspect is useful in the field of foodstuff or the like.

公开(公告)号：US07634776B2

公开(公告)日：2009-12-15

申请号：US11127687

申请日：2005-05-12

申请人： Sankaranarayanan Parameswaran ,  Sriram Sethuraman ,  Manish Singhal ,  Dileep Kumar Tamia ,  Dinesh Kumar ,  Aditya Kulkarni ,  Murali Babu Muthukrishnan

发明人： Sankaranarayanan Parameswaran ,  Sriram Sethuraman ,  Manish Singhal ,  Dileep Kumar Tamia ,  Dinesh Kumar ,  Aditya Kulkarni ,  Murali Babu Muthukrishnan

IPC分类号： G06F9/46 ,  G06F9/30 ,  G06T1/20

CPC分类号： G06F15/7842 ,  H04N19/154 ,  H04N19/436 ,  H04N19/61 ,  H04N19/80

摘要： A method for designing a multi-threaded processing operation that includes, e.g., multimedia encoding/decoding, uses an architecture having multiple processors and optional hardware accelerators. The method includes the steps of: identifying a desired chronological sequence of processing stages for processing input data including identifying interdependencies of said processing stages; allotting each said processing sage to a processor; staggering the processing to accommodate the interdependencies; selecting a processing operation based on said allotting to arrive at a subset of possible pipelines that offer low average processing time; and, choosing one design pipeline from said subset to result in overall timing reduction to complete said processing operation. The invention provides a multi-threaded processing pipeline that is applicable in a System-on-Chip (SoC) using a DSP and shared resources such as DMA controller and on-chip memory, for increasing the throughput. The invention also provides an article which is programmed to execute the method.

摘要翻译： 用于设计包括例如多媒体编码/解码的多线程处理操作的方法使用具有多个处理器和可选硬件加速器的架构。 该方法包括以下步骤：识别用于处理输入数据的处理阶段的期望时间序列，包括识别所述处理阶段的相互依赖性; 将每个所述处理鼠标分配给处理器; 惊ering处理以适应相互依存关系; 基于所述分配来选择处理操作以得到提供较低平均处理时间的可能管线的子集; 并且从所述子集中选择一个设计流水线以产生总体时序减少以完成所述处理操作。 本发明提供了一种多线程处理流水线，其可应用于使用DSP和诸如DMA控制器和片上存储器之类的共享资源的片上系统（SoC），以提高吞吐量。 本发明还提供了一种被编程以执行该方法的物品。

公开(公告)号：US20140188952A1

公开(公告)日：2014-07-03

申请号：US13842997

申请日：2013-03-15

申请人： PRAVEEN KILLAMSETTI ,  Subramaniam Periagaram ,  Aditya Kulkarni

发明人： PRAVEEN KILLAMSETTI ,  Subramaniam Periagaram ,  Aditya Kulkarni

IPC分类号： G06F17/30

CPC分类号： G06F16/172

摘要： A server that caches data in a storage system includes a data access manager that accesses data with a physical location identifier instead of a logical block reference identifier used by a filesystem that manages the cached data. The data access manager provisions a buffer from a pool of buffers maintained by the filesystem, and associates the provisioned buffer with a cache location separate from a buffer cache maintained by the filesystem. The data access manager issues a read for the data with the physical location identifier to obtain the data, and stores the data in the cache location separate from the buffer cache in the provisioned buffer. The data access manager performs a validity check on the obtained data and discards the obtained data when the validity check fails. The data access manager provides access to the buffer to a requesting program.

摘要翻译： 在存储系统中缓存数据的服务器包括数据访问管理器，该数据访问管理器使用物理位置标识符而不是由管理缓存数据的文件系统使用的逻辑块引用标识符来访问数据。 数据访问管理器从由文件系统维护的缓冲池中提供缓冲器，并将所提供的缓冲器与与文件系统维护的缓冲区高速缓存区分开的缓存位置相关联。 数据访问管理器发出具有物理位置标识符的数据的读取以获得数据，并将数据存储在缓存位置中，与缓冲区缓存中的缓冲区高速缓存区分开。 数据访问管理器对获取的数据执行有效性检查，并且在有效性检查失败时丢弃所获得的数据。 数据访问管理器向请求程序提供对缓冲区的访问。

公开(公告)号：US20050262510A1

公开(公告)日：2005-11-24

申请号：US11127687

申请日：2005-05-12

申请人： Sankaranarayanan Parameswaran ,  Sriram Sethuraman ,  Manish Singhal ,  Dileep Tamia ,  Dinesh Kumar ,  Aditya Kulkarni ,  Murali Muthukrishnan

发明人： Sankaranarayanan Parameswaran ,  Sriram Sethuraman ,  Manish Singhal ,  Dileep Tamia ,  Dinesh Kumar ,  Aditya Kulkarni ,  Murali Muthukrishnan

IPC分类号： G06F9/46

CPC分类号： G06F15/7842 ,  H04N19/154 ,  H04N19/436 ,  H04N19/61 ,  H04N19/80

摘要： A method for designing a multi-threaded processing operation that includes, e.g., multimedia encoding/decoding, uses an architecture having multiple processors and optional hardware accelerators. The method includes the steps of: identifying a desired chronological sequence of processing stages for processing input data including identifying interdependencies of said processing stages; allotting each said processing sage to a processor; staggering the processing to accommodate the interdependencies; selecting a processing operation based on said allotting to arrive at a subset of possible pipelines that offer low average processing time; and, choosing one design pipeline from said subset to result in overall timing reduction to complete said processing operation. The invention provides a multi-threaded processing pipeline that is applicable in a System-on-Chip (SoC) using a DSP and shared resources such as DMA controller and on-chip memory, for increasing the throughput. The invention also provides an article which is programmed to execute the method.

摘要翻译： 用于设计包括例如多媒体编码/解码的多线程处理操作的方法使用具有多个处理器和可选硬件加速器的架构。 该方法包括以下步骤：识别用于处理输入数据的处理阶段的期望时间序列，包括识别所述处理阶段的相互依赖性; 将每个所述处理鼠标分配给处理器; 惊ering处理以适应相互依存关系; 基于所述分配来选择处理操作以得到提供较低平均处理时间的可能管线的子集; 并且从所述子集中选择一个设计流水线以产生总体时序减少以完成所述处理操作。 本发明提供了一种多线程处理流水线，其可应用于使用DSP和诸如DMA控制器和片上存储器之类的共享资源的片上系统（SoC），以提高吞吐量。 本发明还提供了一种被编程以执行该方法的物品。

公开(公告)号：US20180318367A1

公开(公告)日：2018-11-08

申请号：US15770620

申请日：2016-10-21

申请人： Kazuhiko SUGIURA ,  Aditya KULKARNI

发明人： Kazuhiko SUGIURA ,  Aditya KULKARNI

IPC分类号： A61K36/185 ,  A23L33/105 ,  A23L2/54 ,  A23G3/48 ,  A23G4/06 ,  A23F5/46 ,  A23G9/42 ,  A23L9/10 ,  A61K31/7034

摘要： A moringa extract containing a benzyl glucosinolate in a content of 6% by mass or more, calculated as a dry solid content of the extract, wherein the extract does not substantially contain an alkaloid. The moringa extract of the present invention for solving a first aspect is useful in the field of foodstuff or the like. Also, the PPAR activator of the present invention for solving a second aspect has excellent PPAR activation action, and has no disadvantages in side effects, so that it can be ingested for long term, which can be preferably used in foodstuff and the like. Therefore, the PPAR activator of the present invention for solving a second aspect can be expected to be used as a food, a supplement or a medicament not only for prevention of disease such as insulin resistance, hyperinsulinism, Type 2 diabetes, hypertension, hyperlipidemia, arterial sclerosis and obesity, but also for fatigue recovery or endurance improvement by improving basal metabolism. In addition, a benzyl glucosinolate-containing composition for solving a third aspect is useful in the field of foodstuff or the like.

公开(公告)号：US20130132701A1

公开(公告)日：2013-05-23

申请号：US13743269

申请日：2013-01-16

申请人： Aditya Kulkarni ,  Sourabh Kukreja

发明人： Aditya Kulkarni ,  Sourabh Kukreja

IPC分类号： G06F12/06

CPC分类号： G06F12/0646 ,  G06N5/022 ,  G06N5/025 ,  G06N5/04 ,  G06Q10/06

摘要： A configuration mapping system and method increase the effectiveness of mapping of information from an established product line to a new product offering. In at least one embodiment, the configuration mapping system herein uses configuration mapping rules to map individual product features and entire configurations from established products to a new product offering. The configuration mapping system also provides a way to appropriately map, for example, demand and sales information for the purpose of demand estimation and sales prediction. Conventionally, mapping can be ineffective because the configuration mapping rules usually focus on one part of the product at a time, and, if applied in isolation, the impact on other parts is missed. The systems and method herein provide a way to integrate configuration mapping rules across feature parts, time periods, and product lines into a unified, holistic view, allowing for new insights.

摘要翻译： 配置映射系统和方法提高了从已建立的产品线到新产品的信息映射的有效性。 在至少一个实施例中，这里的配置映射系统使用配置映射规则来将各个产品特征以及从已建立产品到新产品的整个配置映射。 配置映射系统还提供了一种适当地映射用于需求估计和销售预测的需求和销售信息的方法。 通常，映射可能无效，因为配置映射规则通常集中在产品的一部分上，如果单独应用，则忽略对其他部分的影响。 这里的系统和方法提供了一种将配置映射规则跨功能部件，时间段和产品线整合到统一的整体视图中的方法，从而允许新的见解。