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    Laterally-gated transistors and lateral Schottky diodes with integrated lateral field plate structures
    2.
    发明授权
    Laterally-gated transistors and lateral Schottky diodes with integrated lateral field plate structures 有权

    公开(公告)号：US11967619B2

    公开(公告)日：2024-04-23

    申请号：US17022521

    申请日：2020-09-16

    Applicant: Teledyne Scientific & Imaging, LLC

    Inventor： Keisuke Shinohara ,  Casey King ,  Eric Regan ,  Miguel Urteaga

    IPC: H01L29/40 ,  H01L29/778 ,  H01L29/872

    CPC classification number: H01L29/404 ,  H01L29/778 ,  H01L29/872

    Abstract: Laterally-gated transistors and lateral Schottky diodes are disclosed. The FET includes a substrate, source and drain electrodes, channel, a gate electrode structure, and a dielectric layer. The gate electrode structure includes an electrode in contact with the channel and a lateral field plate adjacent to the electrode. The dielectric layer is disposed between the lateral field plate and the channel. The lateral field plate contacts the dielectric layer and to modulate an electric field proximal to the gate electrode proximal to the drain or source electrodes. Also disclosed is a gate electrode structure with lateral field plates symmetrically disposed relative to the gate electrode. Also disclosed in a substrate with dielectric structures buried in the substrate remote from the gate electrode structure. A lateral Schottky diode having an anode structure includes an anode (A), cathodes (C) and lateral field plates located between the anode and the cathodes.

    Method of forming a bipolar transistor with a vertical collector contact
    9.
    发明授权
    Method of forming a bipolar transistor with a vertical collector contact 有权

    公开(公告)号：US11575020B2

    公开(公告)日：2023-02-07

    申请号：US16908117

    申请日：2020-06-22

    Applicant: Teledyne Scientific & Imaging, LLC

    Inventor： Miguel Urteaga ,  Andy Carter

    IPC: H01L29/417 ,  H01L29/66 ,  H01L21/321 ,  H01L21/8252

    Abstract: A method of forming a bipolar transistor with a vertical collector contact requires providing a transistor comprising a plurality of epitaxial semiconductor layers on a first substrate, and providing a host substrate. A metal collector contact is patterned on the top surface of the host substrate, and the plurality of epitaxial semiconductor layers is transferred from the first substrate onto the metal collector contact on the host substrate. The first substrate is suitably the growth substrate for the plurality of epitaxial semiconductor layers. The host substrate preferably has a higher thermal conductivity than does the first substrate, which improves the heat dissipation characteristics of the transistor and allows it to operate at higher power densities. A plurality of transistors may be transferred onto a common host substrate to form a multi-finger transistor.

    METHOD FOR NEURAL SIGNALS STABILIZATION
    10.
    发明申请
    METHOD FOR NEURAL SIGNALS STABILIZATION 有权

    公开(公告)号：US20220383107A1

    公开(公告)日：2022-12-01

    申请号：US17663031

    申请日：2022-05-12

    Applicant: TELEDYNE SCIENTIFIC & IMAGING, LLC

    Inventor： Stephen B. Simons ,  Mark Alan Peot ,  Thomas Stephens ,  Jon Cafaro ,  Ryan MacRae

    IPC: G06N3/08 ,  G06F3/01

    Abstract: A method for stabilizing disrupted neural signals received by a brain-computer interface (BCI), where a translation model is trained on a clean and disrupted dataset and is used to translate a disrupted signal to a clean signal. The clean dataset is based on the data that is received the same day the BCI is calibrated and the disrupted dataset is based on data received the same day that the model is trained. Based on the variation in daily signal disruption, the training model is retrained each day and a new translation model is applied to a disrupted dataset.

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