公开(公告)号：US08706062B1

公开(公告)日：2014-04-22

申请号：US12421324

申请日：2009-04-09

Applicant: Qian Yu ,  Abhijit G Shanbhag ,  Yan Wang

Inventor： Qian Yu ,  Abhijit G Shanbhag ,  Yan Wang

IPC: H01Q11/12

CPC classification number: H03F3/245 ,  H03F1/3223 ,  H03F1/3247 ,  H03F3/195 ,  H03F3/211 ,  H03F2200/336 ,  H03F2201/3209 ,  H03F2201/3224 ,  H03F2203/21106 ,  H03F2203/21142

Abstract: In one embodiment a mixed-signal adaptive integrated circuit is comprised of a pre-distortion circuit operable to receive an RF input signal and to add a pre-distortion signal to the RF input signal to thereby provide a pre-distorted RF input signal, and a power amplifier coupled to the pre-distortion circuit and operable to receive the pre-distorted RF input signal and to provide an amplified RF output signal. The circuit further comprises a compensation module operable to receive the RF input signal and to provide a compensation signal, an auxiliary amplifier coupled to the compensation module and operable to selectively add the compensation signal to the amplified RF output signal, and a signal analyzer operable to receive and process the RF input signal and an RF output feedback signal to generate a first digital control signal for the pre-distortion circuit and a second digital control signal for the compensation module. A method for adaptive control of such a mixed-signal integrated circuit is also provided.

Abstract translation: 在一个实施例中，混合信号自适应集成电路包括预失真电路，其可操作以接收RF输入信号并将预失真信号添加到RF输入信号，从而提供预失真的RF输入信号，以及 功率放大器，其耦合到所述预失真电路并且可操作以接收所述预失真的RF输入信号并提供放大的RF输出信号。 该电路还包括可操作以接收RF输入信号并提供补偿信号的补偿模块，耦合到补偿模块的辅助放大器，其可操作以选择性地将补偿信号添加到放大的RF输出信号，以及信号分析器，其可操作以 接收和处理RF输入信号和RF输出反馈信号以产生用于预失真电路的第一数字控制信号和用于补偿模块的第二数字控制信号。 还提供了一种用于这种混合信号集成电路的自适应控制的方法。

公开(公告)号：US20140009228A1

公开(公告)日：2014-01-09

申请号：US13954497

申请日：2013-07-30

Applicant: Scintera Networks, Inc.

Inventor： Kelly Davidson HAWKES

IPC: H03F1/32

CPC classification number: H03F1/3247 ,  H03F1/3294 ,  H03F2200/192 ,  H03F2200/195 ,  H03F2200/204 ,  H03F2200/207 ,  H03F2200/228

Abstract: An apparatus and a method select and use parameter values for an RF power amplifier linearizer to pre-distort the input signals of a power amplifier, so as to achieve a linear output response in the power amplifier. The apparatus and the method select from a number of sets of parameter values, each set of parameter values corresponding to a different output power range of the power amplifier. The set of parameters include a coefficient vector tailored for the particular output power range for that set. The power amplifier input power is repeatedly measured and filtered at various time intervals. The input power measurements may be filtered by a fast attack/slow decay filter, which follows the peaks of the measurements under operation of the fast attack portion of the filter and provides a low variance during operation of the slow decay portion of the filter.

Abstract translation: 一种装置和方法选择并使用RF功率放大器线性化器的参数值来预失真功率放大器的输入信号，从而在功率放大器中实现线性输出响应。 该装置和方法从多个参数值集合中选择每一组对应于功率放大器的不同输出功率范围的参数值。 该组参数包括针对该组的特定输出功率范围量身定制的系数向量。 功率放大器输入功率以不同的时间间隔重复测量和滤波。 输入功率测量可以通过快速攻击/慢衰减滤波器来滤波，该滤波器跟随滤波器的快速攻击部分操作的测量的峰值，并且在滤波器的缓慢衰减部分的操作期间提供低的方差。

公开(公告)号：US08519789B2

公开(公告)日：2013-08-27

申请号：US13197691

申请日：2011-08-03

Applicant: Kelly Davidson Hawkes

Inventor： Kelly Davidson Hawkes

IPC: H03F1/26

CPC classification number: H03F1/3247 ,  H03F1/3294 ,  H03F2200/192 ,  H03F2200/195 ,  H03F2200/204 ,  H03F2200/207 ,  H03F2200/228

Abstract: An apparatus and a method select and use parameter values for an RF power amplifier linearizer to pre-distort the input signals of a power amplifier, so as to achieve a linear output response in the power amplifier. The apparatus and the method select from a number sets of parameter values, each set of parameter values corresponding to a different output power range of the power amplifier. The set of parameters include a coefficient vector tailored for the particular output power range for that set. The power amplifier input power is repeatedly measured and filtered at various time intervals. The input power measurements may be filtered by a fast attack/slow decay filter, which follows the peaks of the measurements under operation of the fast attack portion of the filter and provides a low variance during operation of the slow decay portion of the filter. The coefficient values for the predistortion linearization of the power amplifier is adapted dynamically, in response to changes in the input power level of the power amplifier. In one embodiment, hysteresis is used to reduce the rate at which the predistortion linearizer hops between two sets of the parameter values. Using the apparatus and the method, good ACLR across a wide range of power amplifier output power is achieved. Such characteristics are particularly advantageous in a system in which waveforms having fast power transients are present.

Abstract translation: 一种装置和方法选择并使用RF功率放大器线性化器的参数值来预失真功率放大器的输入信号，从而在功率放大器中实现线性输出响应。 该装置和方法从多组参数值中选择每组与功率放大器的不同输出功率范围对应的参数值。 该组参数包括针对该组的特定输出功率范围量身定制的系数向量。 功率放大器输入功率以不同的时间间隔重复测量和滤波。 输入功率测量可以通过快速攻击/慢衰减滤波器来滤波，该滤波器跟随滤波器的快速攻击部分操作的测量的峰值，并且在滤波器的缓慢衰减部分的操作期间提供低的方差。 响应于功率放大器的输入功率电平的变化，功率放大器的预失真线性化的系数值被动态地适配。 在一个实施例中，使用滞后来降低预失真线性化器在两组参数值之间跳跃的速率。 使用该装置和方法，实现了广泛的功率放大器输出功率的良好的ACLR。 在存在具有快速功率瞬变的波形的系统中，这种特性是特别有利的。

公开(公告)号：US08331487B2

公开(公告)日：2012-12-11

申请号：US12939067

申请日：2010-11-03

Applicant: Qian Yu ,  Frédéric Roger ,  Adric Q. Broadwell ,  Olivier Charlon

Inventor： Qian Yu ,  Frédéric Roger ,  Adric Q. Broadwell ,  Olivier Charlon

IPC: H04K1/02 ,  H04L25/03 ,  H04L25/49

CPC classification number: H03F1/3241 ,  H03F3/19 ,  H03F2201/3224 ,  H04B2001/0425

Abstract: RF predistortion apparatus for making linear the output signal of non-linear components such as RF power amplifiers. The apparatus comprises an RF input line for carrying an RF signal connected to an envelope detector for finding the envelope of the RF signal, a power detector for finding the power of the RF signal and a quadrature modulator. The apparatus also comprises a coefficient vector input line for carrying an input signal that carries one or more coefficients to a digitally controlled analog subsystem (DCAS). The DCAS having circuitry for processing both the output of the envelope detector and the output of the power detector by selecting one or more coefficients from the coefficient vector input line for generating a weighted summation of the power of the RF signal and a weighted summation of the envelope voltage of the RF signal that are output to the quadrature modulator. The quadrature modulator has circuitry for mixing the RF input signal with the output of the DCAS to generate a signal for predistorting the RF input signal feeding the power amplifier.

Abstract translation: 射频预失真装置，用于对诸如RF功率放大器之类的非线性分量的输出信号进行线性化。 该装置包括用于携带连接到包络检测器的RF信号的RF输入线，用于找到RF信号的包络，用于找到RF信号的功率的功率检测器和正交调制器。 该装置还包括一个用于承载一个或多个系数到数字控制的模拟子系统（DCAS）的输入信号的系数向量输入线。 DCAS具有用于通过从系数向量输入线中选择一个或多个系数来处理包络检测器的输出和功率检测器的输出的电路，用于产生RF信号的功率的加权求和和 输出到正交调制器的RF信号的包络电压。 正交调制器具有用于将RF输入信号与DCAS的输出混合以产生用于预失真馈送功率放大器的RF输入信号的信号的电路。

公开(公告)号：US08295394B1

公开(公告)日：2012-10-23

申请号：US12257292

申请日：2008-10-23

Applicant: Adric Q. Broadwell ,  Armando C. Cova ,  Frederic Roger ,  Qian Yu

Inventor： Adric Q. Broadwell ,  Armando C. Cova ,  Frederic Roger ,  Qian Yu

IPC: H04K1/02

CPC classification number: H03F1/3247 ,  H03F2201/3224

Abstract: A performance monitor for generating a digital error signal based upon an RF input signal and an amplified RF output signal is provided. The monitor includes: a first analog-to-digital converter operable to digitize an in-phase (I) and a quadrature-phase (Q) version of the RF input signal responsive to a first clock signal to provide a first digital I signal and a first digital Q signal; a second analog-to-digital converter operable to digitize an in-phase (I) and a quadrature-phase version of the amplified RF output signal responsive to a second clock signal to provide a second digital I signal and a second digital Q signal; a first adaptive delay filter to delay the first digital I signal and the first digital Q signal to provide a first delayed complex signal according to a first delay; a second adaptive filter to delay the second digital I signal and the second digital Q signals to provide a second delayed complex signal according to a second delay; a complex gain matching adder operable to add a complex gain matching factor to a selected one of the delayed complex signals to provide a gain matched complex signal; and an adder to add the gain matched complex signal to a remaining one of the first and second delayed complex signals to provide the digital error signal.

Abstract translation: 提供了一种用于基于RF输入信号和放大的RF输出信号产生数字误差信号的性能监视器。 监视器包括：第一模数转换器，用于响应于第一时钟信号数字化RF输入信号的同相（I）和正交相位（Q）版本，以提供第一数字I信号和 第一数字Q信号; 第二模数转换器，用于响应于第二时钟信号数字化放大的RF输出信号的同相（I）和正交相位版本，以提供第二数字I信号和第二数字Q信号; 第一自适应延迟滤波器，用于延迟第一数字I信号和第一数字Q信号，以根据第一延迟提供第一延迟复信号; 第二自适应滤波器，用于延迟所述第二数字I信号和所述第二数字Q信号，以根据第二延迟提供第二延迟复信号; 复增益匹配加法器，用于将复增益匹配因子添加到所选延迟复信号中的一个以提供增益匹配复信号; 以及加法器，用于将增益匹配复信号与第一和第二延迟复数信号中的剩余的一个相加，以提供数字误差信号。

公开(公告)号：US08229027B2

公开(公告)日：2012-07-24

申请号：US12909649

申请日：2010-10-21

Applicant: Arvind Keerthi ,  Madabusi Govindarajan ,  P. Vijay Kumar ,  John Choma ,  Abhijit Shanbhag

Inventor： Arvind Keerthi ,  Madabusi Govindarajan ,  P. Vijay Kumar ,  John Choma ,  Abhijit Shanbhag

IPC: H04K1/02 ,  H04L25/03 ,  H04L25/49

CPC classification number: H04L27/368 ,  H03F1/0222 ,  H03F1/0266 ,  H03F1/3211 ,  H03F1/3247 ,  H03F1/3258 ,  H03F3/45183 ,  H03F2200/102 ,  H03F2200/369 ,  H03F2200/451 ,  H03F2203/45352

Abstract: Pre-distortion and memory compensation apparatuses and methods for a non-linear component are provided. The apparatus comprises an adaptive block for generating a plurality of correlation coefficients, which are used to weight a plurality of synthesis work functions to pre-distort a given signal. The adaptive block can be driven by an error signal generated from a feedback signal from the non-linear component output signal and a delayed version of the input signal. The apparatus is capable of being operated directly at radio frequency. Also provided are apparatuses and methods for generation of quadrature signals, transconductance amplification employing negative resistance, variable-gain amplification, and envelope detection.

Abstract translation: 提供了用于非线性分量的预失真和存储器补偿装置和方法。 该装置包括用于产生多个相关系数的自适应块，其用于加权多个合成工作函数以对给定信号进行预失真。 自适应块可以由从非线性分量输出信号的反馈信号和输入信号的延迟版本产生的误差信号驱动。 该装置能够以射频直接操作。 还提供了用于产生正交信号，采用负电阻的跨导放大，可变增益放大和包络检测的装置和方法。

公开(公告)号：US08145150B1

公开(公告)日：2012-03-27

申请号：US12340032

申请日：2008-12-19

Applicant: Qian Yu ,  Abhijit G. Shanbhag ,  Yan Wang

Inventor： Qian Yu ,  Abhijit G. Shanbhag ,  Yan Wang

IPC: H04B1/04

CPC classification number: H03F1/3241 ,  H03F1/3247 ,  H04B17/13

Abstract: A mixed-signal adaptive integrated circuit may comprise a primary function circuit, a digitally controlled analog sub-system cooperatively connected with the primary function circuit, and an on-chip signal analyzer. The on-chip signal analyzer may be arranged to analyze RF signals. The signal analyzer may comprise at least one multiplexor for selecting selected RF signals for comparison and analysis, and may comprise a digital signal processor (DSP) for analyzing the selected RF signals and adjusting at least one operational parameter of the digitally controlled analog sub-system responsive to the analysis.

Abstract translation: 混合信号自适应集成电路可以包括与主要功能电路协作连接的主要功能电路，数字控制的模拟子系统和片上信号分析器。 片上信号分析器可以被布置成分析RF信号。 信号分析器可以包括用于选择用于比较和分析的所选RF信号的至少一个多路复用器，并且可以包括用于分析所选择的RF信号并调整数字控制的模拟子系统的至少一个操作参数的数字信号处理器（DSP） 响应分析。

公开(公告)号：US07627031B2

公开(公告)日：2009-12-01

申请号：US11186241

申请日：2005-07-21

Applicant: Qian Yu ,  Venugopal Balasubramonian ,  Jishnu Bhattacharjee ,  Debanjan Mukherjee ,  Abhijit Phanse ,  Abhijit G. Shanbhag ,  Edem Ibragimov ,  Fabian Giroud

Inventor： Qian Yu ,  Venugopal Balasubramonian ,  Jishnu Bhattacharjee ,  Debanjan Mukherjee ,  Abhijit Phanse ,  Abhijit G. Shanbhag ,  Edem Ibragimov ,  Fabian Giroud

IPC: H03H7/30

CPC classification number: H04L7/0062 ,  H04L7/0029 ,  H04L25/03057 ,  H04L2025/03503

Abstract: An apparatus and method for adaptively introducing a compensating signal latency related to a signal latency of a data symbol decision circuit. Adaptive timing control circuitry, including an interpolating mixer implemented as a tapped delay line with correlated tap coefficients, introduces a latency adaptively and substantially matching the latency of the data decision circuit for use within an adaptive equalizer, thereby minimizing the mean-squared error of such decision circuit. This adaptive latency is used in generating the feedback error signal which, in turn, can be used by the feedforward equalizer for dynamically adjusting its adaptive filter tap coefficients.

Abstract translation: 一种用于自适应地引入与数据符号判定电路的信号等待时间相关的补偿信号延迟的装置和方法。 自适应定时控制电路，包括实现为具有相关抽头系数的抽头延迟线的内插混频器，自适应地和基本上匹配数据判决电路的等待时间以在自适应均衡器内使用，从而最小化这样的均方误差 决策电路。 该自适应等待时间用于产生反馈误差信号，反馈误差信号又可由前馈均衡器用于动态调整其自适应滤波器抽头系数。

公开(公告)号：US07394849B2

公开(公告)日：2008-07-01

申请号：US11539810

申请日：2006-10-09

Applicant: Edem Ibragimov ,  Qian Yu ,  Prashant Choudhary

Inventor： Edem Ibragimov ,  Qian Yu ,  Prashant Choudhary

IPC: H03H7/30 ,  H03H7/40 ,  H03K5/159

CPC classification number: H04L25/03057 ,  H03H21/0012 ,  H03H2021/0096 ,  H04L25/03063 ,  H04L25/0307 ,  H04L2025/0349 ,  H04L2025/03509 ,  H04L2025/03611

Abstract: A decision feedback equalizer with dynamic feedback control for use in an adaptive signal equalizer. Timing within the decision feedback loop is dynamically controlled to optimize recovery of the data signal by the output signal slicer. The dynamic timing is controlled by a signal formed as a combination of feedback and feedforward signals. The feedback signal is an error signal related to a difference between pre-slicer and post-slicer signals. The feedforward signal is formed by differentiating and delaying the incoming data signal.

Abstract translation: 具有用于自适应信号均衡器的动态反馈控制的判决反馈均衡器。 动态控制决策反馈环路内的定时，以优化输出信号限幅器对数据信号的恢复。 动态定时由形成为反馈和前馈信号的组合的信号控制。 反馈信号是与预切片器和后切片器信号之间的差异相关的误差信号。 前馈信号通过差分和延迟输入数据信号来形成。

公开(公告)号：US07130366B2

公开(公告)日：2006-10-31

申请号：US10290674

申请日：2002-11-08

Applicant: Abhijit Phanse ,  Abhijit G. Shanbhag

Inventor： Abhijit Phanse ,  Abhijit G. Shanbhag

IPC: H04B1/00

CPC classification number: H04L25/03057 ,  H04B10/6971 ,  H04L25/03038 ,  H04L25/03878 ,  H04L2025/03624 ,  H04L2025/03656 ,  H04L2025/037

Abstract: A compensation circuit and method for reducing ISI products within an electrical data signal corresponding to a detected data signal received via a signal transmission medium introduces distinct compensation effects for individual ISI products within the electrical data signal. Distinct data signal components within the detected data signal and corresponding to such ISI products can be selectively and individually compensated, thereby producing a compensated data signal in which each selected one of such individual data signal components is substantially removed. Individual data signal components or selected combinations of data signal components can be compensated as desired.