公开(公告)号：US20240387718A1

公开(公告)日：2024-11-21

申请号：US18320063

申请日：2023-05-18

Applicant: GAN SYSTEMS INC.

Inventor： Claudio Andres Canizares

IPC: H01L29/778 ,  H01L29/10 ,  H01L29/20

Abstract: A heterojunction structure in which a barrier semiconductor layer is epitaxially grown on a channel semiconductor layer but varying a composition of the barrier semiconductor layer for at least part of the epitaxial growth of the barrier semiconductor layer. By so doing, in some cases, a free electron density in planar view of the 2 DEG may be increased thereby allowing for greater current flow for a given voltage difference. Furthermore, for a given current, the mobility of the electrons is increased, thus reducing the on resistance of transistors that include the 2 DEG as a channel region. This further improves power efficiency of the transistor, and reduces heat generated by the transistor at a given power.

公开(公告)号：US20240372478A1

公开(公告)日：2024-11-07

申请号：US18310416

申请日：2023-05-01

Applicant: GAN SYSTEMS INC.

Inventor： Mahdi JEDARI ZARE ZADEH ,  Juncheng LU

IPC: H02M3/335 ,  H02M1/00 ,  H02M7/483

Abstract: A voltage converter circuit including a primary side circuit including four transistors connected in series between two voltage application nodes, and two capacitors coupled in series between the two voltage application nodes. A flying capacitor is connected between first circuit node and a second circuit node, where the first circuit node is between the first and second transistors in the transistor series, and the second circuit node is between the third and fourth transistors in the transistor series. A primary side transformer is connected between a third circuit node and a fourth circuit node, where the third circuit node is between the second and third transistors in the transistor series, and the fourth circuit node is between the first and second capacitors in the capacitor series.

公开(公告)号：US20240332368A1

公开(公告)日：2024-10-03

申请号：US18129457

申请日：2023-03-31

Applicant: GaN Systems Inc.

Inventor： Vineet Unni ,  Thomas MacElwee

IPC: H01L29/20 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/2003 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7786

Abstract: A GaN semiconductor power transistor structure with a stepped gate field plate, and a method of fabrication is disclosed. The stepped gate field plate is formed using contact metal and/or interconnect metal. The stepped structure of the gate field plate is defined by dielectric etching to form openings for the stepped gate field plate, and the dielectric thickness under the gate field plate is sized and stepped to shape appropriately the electric field in the region between the gate and drain. The resulting stepped gate field plate structure is less sensitive to limitations of stepped field plates fabricated by a lift-off metal process.

公开(公告)号：US20240213125A1

公开(公告)日：2024-06-27

申请号：US18085684

申请日：2022-12-21

Applicant: GaN Systems Inc.

Inventor： Abhinandan DIXIT

IPC: H01L23/495 ,  H01L23/29 ,  H01L23/31

CPC classification number: H01L23/49565 ,  H01L23/295 ,  H01L23/3107

Abstract: Embedded die packaging for high voltage, high temperature operation of power semiconductor switching devices is disclosed, wherein a power semiconductor die is mounted on a leadframe and embedded in laminated body comprising a layer stack of a plurality of dielectric layers and electrically conductive layers. Electrical connections between contact pads of the power semiconductor die and external contact pads of the package comprise conductive vias extending through the dielectric layers. Edges of the leadframe are structured to provide vertical and lateral interlocking of the leadframe with surrounding dielectric, e.g. by providing a leadframe having a laterally scalloped and vertically undercut edge structure. Edges of the leadframe may be beveled.

公开(公告)号：US20240213110A1

公开(公告)日：2024-06-27

申请号：US18085660

申请日：2022-12-21

Applicant: GaN Systems Inc.

Inventor： An-Sheng CHENG ,  Stephen COATES

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/495 ,  H01L23/522 ,  H01L23/528 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L23/3192 ,  H01L21/4828 ,  H01L21/56 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/49513 ,  H01L23/49562 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/32 ,  H01L29/401 ,  H01L29/41775 ,  H01L2224/32225 ,  H01L2924/1033 ,  H01L2924/13064

Abstract: Embedded die packaging for semiconductor power switching devices, wherein the package comprises a laminated body comprising a layer stack of a plurality of dielectric layers and conductive metal layers. A thermal contact area on a back-side of the die is attached to a leadframe. A patterned layer of conductive metallization on a front-side of the die provides electrical contact areas of the power semiconductor device. Before embedding, a protective dielectric layer is provided on the front-side of the die, extending around edges of the die. The protective dielectric layer provides a protective region that acts a cushion to protect edges of the die from damage during lamination. The protective dielectric material may extend over the electrical contact areas to protect against etch damage and damage during laser drilling of vias, thereby mitigating physical damage, overheating or other potential damage to the active region of the semiconductor device.

公开(公告)号：US11776883B2

公开(公告)日：2023-10-03

申请号：US17728220

申请日：2022-04-25

Applicant: GaN Systems Inc.

Inventor： Cameron McKnight-MacNeil ,  Greg P. Klowak

IPC: H01L23/495 ,  H01L23/482 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  H01L29/20 ,  H01L29/778 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49503 ,  H01L23/3107 ,  H01L23/4824 ,  H01L23/49844 ,  H01L23/5226 ,  H01L23/53228 ,  H01L24/18 ,  H01L29/2003 ,  H01L29/778 ,  H01L2224/04105 ,  H01L2224/82 ,  H01L2924/13091

Abstract: Embedded die packaging for high voltage, high temperature operation of power semiconductor devices is disclosed, wherein a power semiconductor die is embedded in laminated body comprising a layer stack of a plurality of dielectric layers and electrically conductive layers. For example, the dielectric layers comprise dielectric build-up layers of filled or fiber reinforced dielectric and conductive interconnect comprises copper layers and copper filled vias. A dielectric build-up layer, e.g. filled or glass fiber reinforced epoxy, forms an external surface of the package covering underlying copper interconnect, particularly in regions which experience high electric field during operation, such as between closely spaced source and drain interconnect metal. For example, the power semiconductor device comprises a GaN HEMT rated for operation at ≥100V wherein the package body has a laminated structure configured for high voltage, high temperature operation with improved reliability.

公开(公告)号：US20230282540A1

公开(公告)日：2023-09-07

申请号：US17979970

申请日：2022-11-03

Applicant: GaN Systems Inc.

Inventor： Ruoyu HOU ,  Juncheng LU ,  Andrew DICKSON

IPC: H01L23/367 ,  H01L23/373 ,  H01L25/07 ,  H01L29/20

CPC classification number: H01L23/3672 ,  H01L23/3735 ,  H01L23/3731 ,  H01L25/072 ,  H01L29/2003

Abstract: A multi-zone substrate for a power stage assembly comprising at least one bottom-cooled semiconductor power switching device and driver components, for integration on a common substrate. A first zone provides electrical connections and a thermal pad for mounting at least one bottom-cooled semiconductor switching device, the first zone comprising dielectric and conductive layers which provide a power substrate optimized for thermal performance. A second zone provides electrical connections for mounting driver components, the second zone comprising dielectric and conductive layers providing a driver substrate optimized for electrical performance. For example, the first zone comprises a single layer metal interconnect structure with a first thermal resistance, the second zone comprises a multi-layer metal interconnect structure with a second thermal resistance, the first thermal resistance being less than the second thermal resistance. The power stage assembly may comprise a multi-zone substrate configured for a single switch, half-bridge or full-bridge switch topology.

公开(公告)号：US11545889B2

公开(公告)日：2023-01-03

申请号：US17536542

申请日：2021-11-29

Applicant: GaN Systems Inc.

Inventor： Yajie Qiu ,  Larry Spaziani

IPC: H02M1/38

Abstract: Disclosed is a method for deadtime optimization in a half-bridge switch or full-bridge switch wherein high-side and low-side switches comprise GaN transistors; a circuit for implementing the method; and a power switching system comprising a GaN half-bridge or a GaN full-bridge and a deadtime optimization system. The circuit comprises a drain current bump filter for generating a current charge output; and circuit elements for comparing the current charge output to a reference current charge Coss and generating a deadtime adjust signal. The deadtime adjust signal may be used to adjust deadtime to reduce or minimize deadtime, and deadtime losses, while avoiding cross-conduction.

公开(公告)号：US20220385195A1

公开(公告)日：2022-12-01

申请号：US17881203

申请日：2022-08-04

Applicant: GaN Systems Inc.

Inventor： Xuechao LIU ,  Paul WIENER

IPC: H02M3/335 ,  H02M3/158 ,  H02M1/42 ,  H02M1/00

Abstract: An architecture for a multi-port AC/DC Switching Mode Power Supply (SMPS) with Power Factor Correction (PFC) comprises power management control (PMC) for PFC On/Off Control and Smart Power Distribution, and optionally, a boost follower circuit. For example, in a universal AC/DC multi-port USB-C Power Delivery (PD) adapter, PMC enables turn-on and turn-off of PFC dependent on output port operational status and a combined load of active output ports. A microprocessor control unit (MCU) receives operational status, a voltage sense input and a current sense input for each USB port, computes output power for each USB port, and executes a power distribution protocol to turn-on or turn-off PFC dependent on the combined load from each USB port. Available power may be distributed intelligently to one or more ports, dependent on load. In an example embodiment, turning-off PFC for low load and low AC line input increases efficiency by 3% to 5%.

公开(公告)号：US20210217884A1

公开(公告)日：2021-07-15

申请号：US17213665

申请日：2021-03-26

Applicant: GaN Systems Inc.

Inventor： Thomas MACELWEE

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L21/02

Abstract: GaN HEMT device structures and methods of fabrication are provided. A dielectric layer forms a p-dopant diffusion barrier, and low temperature selective growth of p-GaN within a gate slot in the dielectric layer reduces deleterious effects of out-diffusion of p-dopant into the 2DEG channel. A structured AlxGa1-xN barrier layer includes a first thickness having a first Al %, and a second thickness having a second Al %, greater than the first Al %. At least part of the second thickness of the AlxGa1-xN barrier layer in the gate region is removed, before selective growth of p-GaN in the gate region. The first Al % and first thickness are selected to determine the threshold voltage Vth and the second Al % and second thickness are selected to determine the Rdson and dynamic Rdson of the GaN HEMT, so that each may be separately determined to improve device performance, and provide a smaller input FOM (Figure of Merit).