公开(公告)号：US20050273534A1

公开(公告)日：2005-12-08

申请号：US11192561

申请日：2005-07-29

申请人： Dwight Riley ,  Christopher Pettey

发明人： Dwight Riley ,  Christopher Pettey

IPC分类号： G06F13/00 ,  G06F13/36 ,  G06F13/40

CPC分类号： G06F13/4027 ,  G06F13/405

摘要： A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port (“AGP”) bus and host and memory buses, as a bridge between an additional registered peripheral component interconnect (“RegPCI”) bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional RegPCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an additional registered PCI bus bridge is to be implemented. The multiple use core logic chip set has an arbiter having Request (“REQ”) and Grant (“GNT”) signal lines for each PCI device utilized on the additional registered PCI bus. Selection of the type of bus bridge (AGP or RegPCI) in the multiple use core logic chip set may be made by a hardware signal input, or by software during computer system configuration or power on self test (“POST”). Software configuration may also be determined upon detection of either an AGP or a RegPCI device connected to the common AGP/RegPCI bus.

摘要翻译： 在可以被配置为加速图形端口（“AGP”）总线与主机与存储器总线之间的桥接的计算机系统中提供了多用途核心逻辑芯片组，作为附加的注册的外围组件互连（“ RegPCI“）总线和主机和内存总线，或作为主PCI总线和附加RegPCI总线之间的桥梁。 多用途芯片组的功能是在计算机系统的制造时或在现场确定是否要实现AGP总线桥接器或附加的注册PCI总线桥接器。 多用核心逻辑芯片组具有仲裁器，其具有针对在附加的已注册PCI总线上使用的每个PCI设备的请求（“REQ”）和Grant（“GNT”）信号线。 可以通过硬件信号输入或在计算机系统配置或上电自检（“POST”）期间通过软件来选择多用途核心逻辑芯片组中的总线桥（AGP或RegPCI）类型。 也可以在检测到连接到公共AGP / RegPCI总线的AGP或RegPCI设备时确定软件配置。

公开(公告)号：US20050033893A1

公开(公告)日：2005-02-10

申请号：US10945003

申请日：2004-09-20

申请人： Christopher Pettey ,  Dwight Riley

发明人： Christopher Pettey ,  Dwight Riley

IPC分类号： G06F13/00 ,  G06F13/36 ,  G06F13/40

CPC分类号： G06F13/4027 ,  G06F13/405

摘要： **A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port (“AGP”) bus and host and memory buses, as a bridge between an additional registered peripheral component interconnect (“RegPCI”) bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional RegPCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an additional registered PCI bus bridge is to be implemented. The multiple use core logic chip set has an arbiter having Request (“REQ”) and Grant (“GNT”) signal lines for each PCI device utilized on the additional registered PCI bus. Selection of the type of bus bridge (AGP or RegPCI) in the multiple use core logic chip set may be made by a hardware signal input, or by software during computer system configuration or power on self test (“POST”). Software configuration may also be determined upon detection of either an AGP or a RegPCI device connected to the common AGP/RegPCI bus.

摘要翻译： **在可以配置为加速图形端口（“AGP”）总线与主机和存储器总线之间的桥接器的计算机系统中提供了多用途核心逻辑芯片组，作为附加注册的外围组件互连 （“RegPCI”）总线和主机和内存总线，或作为主PCI总线和附加RegPCI总线之间的桥梁。 多用途芯片组的功能是在计算机系统的制造时或在现场确定是否要实现AGP总线桥接器或附加的注册PCI总线桥接器。 多用核心逻辑芯片组具有仲裁器，其具有针对在附加的已注册PCI总线上使用的每个PCI设备的请求（“REQ”）和Grant（“GNT”）信号线。 可以通过硬件信号输入或在计算机系统配置或上电自检（“POST”）期间通过软件来选择多用途核心逻辑芯片组中的总线桥（AGP或RegPCI）类型。 也可以在检测到连接到公共AGP / RegPCI总线的AGP或RegPCI设备时确定软件配置。

公开(公告)号：US20020149461A1

公开(公告)日：2002-10-17

申请号：US10167944

申请日：2002-06-11

申请人： Compaq Computer Corporation

发明人： Raoji A. Patel ,  James E. Drew ,  Raymond A. Pelletier ,  Brian R. McQuain

IPC分类号： H01F005/00

CPC分类号： H01F27/2804 ,  H01F41/041 ,  H01F2019/085 ,  H05K1/165 ,  Y10T29/4902

摘要： A method and apparatus to layout planar magnetic coils on a PCB consists of maximizing the layer to layer overlap, and consequently maximizing total inductance for the given layout area, by spiraling alternating layers inward and outward. A further benefit of the matching opposite spirals is the ability to make the layer to layer electrical contacts within the magnetic field area, thus reducing leakage inductance, and minimizing the wasted extra conductor line length needed to make the connections outside the magnetic field. The reduced conductor line length results in reduced conductor line resistance. The method is applicable to voltage transformers and isolation transformers as well as simple inductors and other magnetic devices. In the transformer case the odd numbered layers are typically connected together in series to provide a larger turn ratio, and the even numbered layers are typically single turns (i.e., no spiral) connected together in parallel to provide more current capability.

公开(公告)号：US20020143839A1

公开(公告)日：2002-10-03

申请号：US10016902

申请日：2001-12-14

申请人： Compaq Computer Corporation

发明人： Mark D. Matson ,  Robert J. Dupcak ,  Jonathan D. Krause ,  Sridhar Samudrala

IPC分类号： G06F007/38

CPC分类号： G06F7/535 ,  G06F7/4824 ,  G06F7/508 ,  G06F7/5525 ,  G06F9/3814 ,  G06F9/3838 ,  G06F9/384 ,  G06F2207/5352

摘要： The invention provides computer apparatus for performing a square root or division operation generating a root or quotient. A partial remainder is stored in radix-2 or radix-4 signed digit format. A decoder is provided for computing a root or quotient digit, and a correction term dependent on a number of the most significant digits of the partial remainder. An adder is provided for computing the sum of the signed digit partial remainder and the correction term in binary format, and providing the result in signed digit format. The adder computes a carry out independent of a carry in bit and a sum dependent on a Carry_in bit providing a fast adder independent of carry propagate delays. The scaler performs a multiplication by two of the result output from the adder in signed digit format to provide a signed digit next partial remainder.

公开(公告)号：US20020089829A1

公开(公告)日：2002-07-11

申请号：US10098105

申请日：2002-03-14

申请人： COMPAQ COMPUTER CORPORATION

发明人： Juan M. Perez ,  Jeffrey A. Lambert ,  Donald J. Hall

IPC分类号： H05K005/00 ,  H05K005/04 ,  H05K005/06

CPC分类号： G06F1/184 ,  G06F1/18 ,  H05K7/142 ,  H05K7/1429

摘要： A screwless technique for mounting a circuit board in a computer chassis is provided in which circular portions of keyhole-shaped mounting openings in the circuit board body are first moved downwardly over notched chassis mounting bosses. The circuit board is then forwardly moved transversely to the bosses to move opening edge portions of the circuit board body into the boss notches in a manner releasably preventing the circuit board from being lifted off the bosses. A retaining bracket is placed adjacent a body edge of the installed circuit board to block the board against rearward releasing movement relative to the chassis bosses.

公开(公告)号：US20020059533A1

公开(公告)日：2002-05-16

申请号：US10039983

申请日：2001-10-19

申请人： Compaq Computer Corporation

发明人： George A. Kaminski ,  George F. Squibb

IPC分类号： G06F001/26

CPC分类号： H05K7/20209 ,  G06F1/206 ,  Y02D10/16

摘要： A method and system for controlling the power supply fan in a computer system. The speed of a power supply fan can be made directly proportional to the temperature of the power supply. The fan speed can also be controlled by a processor with software commands according to the temperature of the processor. The speed of the fan will be dictated by the higher of the two commands driving it. Therefore, the power supply fan can never be commanded by the processor to run at a lower speed than that required by its own thermal environment. A Fan Speed Control Circuit enables the computer system to command the power supply fan to run at a higher speed. The processor temperature can be monitored with a temperature transducer and analog signal conditioning circuitry.

摘要翻译： 一种用于控制计算机系统中的电源风扇的方法和系统。 电源风扇的速度可以与电源的温度成正比。 风扇速度也可以由具有根据处理器温度的软件命令的处理器控制。 风扇的速度将由驱动它的两个命令中的较高者决定。 因此，电源风扇永远不能被处理器命令以比其自身热环境所要求的速度更低的速度运行。 风扇速度控制电路使计算机系统能够使电源风扇以更高的速度运行。 可以使用温度传感器和模拟信号调理电路来监控处理器温度。

公开(公告)号：US6167509A

公开(公告)日：2000-12-26

申请号：US243559

申请日：1994-05-16

申请人： Richard Lee Sites ,  Richard T. Witek

发明人： Richard Lee Sites ,  Richard T. Witek

IPC分类号： G06F9/30 ,  G06F9/315 ,  G06F9/38 ,  G06F9/00

CPC分类号： G06F9/30072 ,  G06F9/30 ,  G06F9/30032 ,  G06F9/30167 ,  G06F9/3806 ,  G06F9/3846

摘要： A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Performance can be speeded up by predicting the target of a branch and prefetching the new instruction based upon this prediction; a branch prediction rule is followed that requires all forward branches to be predicted not-taken and all backward branches (as is common for loops) to be predicted as taken. Another performance improvement makes use of unused bits in the standard. sized instruction to provide a hint of the expected target address for jump and jump to subroutine instructions or the like. The target can thus be prefetched before the actual address has been calculated and placed in a register. In addition, the unused displacement part of the jump instruction can contain a field to define the actual type of jump, i.e., jump, jump to subroutine, return from subroutine, and thus place a predicted target address in a stack to allow prefetching before the instruction has been executed.

摘要翻译： RISC（精简指令集）类型的高性能CPU采用标准化的固定指令大小，并且仅允许简化的存储器访问数据宽度和寻址模式。 指令集仅限于寄存器到寄存器操作和寄存器加载/存储操作。 可以通过预测分支的目标并基于该预测来预取新指令来加快性能; 遵循分支预测规则，要求将所有前向分支预测为未被采用，并且所有后向分支（如循环常用）被预测为采用。 另一个性能改进使得在标准中使用未使用的位。 提供预期目标地址的提示以跳转和跳转到子程序指令等。 因此，可以在实际地址被计算并放置在寄存器中之前预取目标。 此外，跳转指令的未使用的位移部分可以包含一个字段来定义跳转的实际类型，即跳转，跳转到子程序，从子程序返回，从而将预测的目标地址放在堆栈中，以便在 指令已执行。

公开(公告)号：US6154804A

公开(公告)日：2000-11-28

申请号：US250232

申请日：1999-02-15

申请人： Javier F. Izquierdo ,  John A. Landry

发明人： Javier F. Izquierdo ,  John A. Landry

IPC分类号： G06F12/02 ,  G06F12/08 ,  G06F15/17 ,  G06F13/00

CPC分类号： G06F15/17 ,  G06F12/0284 ,  G06F12/0806

摘要： A method for communication between multiple processors using registers that are accessed by four register select lines which are translated from the original system address. The address translation is performed off of the main processor board to reduce loading effects on the local bus and reduces the pin count of processor board. A signal representing which of the processors is currently active is used as a pseudo address line for the purpose of the translation. The original addresses of the I/O registers may be either input/output or memory mapped.

摘要翻译： 一种使用由原始系统地址翻译的四个寄存器选择线访问的寄存器的多个处理器之间进行通信的方法。 地址转换是从主处理器板执行的，以减少对本地总线的负载影响，并减少处理器板的引脚数。 代表处理器当前处于活动状态的信号被用作用于转换目的的伪地址线。 I / O寄存器的原始地址可以是输入/输出或存储器映射。

公开(公告)号：US6151401A

公开(公告)日：2000-11-21

申请号：US057841

申请日：1998-04-09

申请人： Marco Annaratone

发明人： Marco Annaratone

IPC分类号： H04R5/02 ,  H04R25/00

CPC分类号： G06F1/1688 ,  G06F1/1616 ,  G06F1/1624 ,  H04R5/02

摘要： A portable computer system with planar speakers. The planar speakers are fabricated with a coplanar array of small, low cost, durable, electromagnetic speaker elements mounted on a panel. The planar speakers can be attached to the lid of the computer system. The planar speakers can slide into a compartment in the lid of the computer system when not in use and slide out of the compartment for use with greater physical separation than that of built-in speakers. Alternatively, the planar speakers are attached to the lid via a hinge and folded against the lid when not in use. The planar speakers are folded outward extending the planar speakers beyond the lid for use with greater physical separation than that of built-in speakers. The planar speakers can be detachable from the remainder of the computer system for greater spacing and variable positioning of the planar speakers for improved stereo sound reproduction. Detached planar speakers also permit transport or storage of the planar speakers separately from the remainder of the computer system. Such planar speakers also have application in portable music reproduction devices and, in larger area form, for use in home audio systems.

摘要翻译： 具有平面扬声器的便携式计算机系统。 平面扬声器由安装在面板上的小型，低成本，耐用的电磁扬声器元件的共面阵列制造。 平面扬声器可以连接到计算机系统的盖子上。 当不使用时，平面扬声器可以滑入计算机系统的盖子中的一个隔间，并从室内滑出，比内置扬声器更大的物理分离使用。 或者，平面扬声器通过铰链附接到盖子，并且在不使用时折叠在盖子上。 平面扬声器向外折叠，将平面扬声器向外延伸超过盖，用于比内置扬声器更大的物理分离。 平面扬声器可以与计算机系统的其余部分分离，用于平面扬声器的更大间隔和可变定位，以改善立体声再生。 独立的平面扬声器还允许平面扬声器与计算机系统的其余部分分开运输或存储。 这样的平面扬声器也可用于便携式音乐再现设备中，并且在较大的区域形式中也可用于家用音频系统。

公开(公告)号：US6151218A

公开(公告)日：2000-11-21

申请号：US137592

申请日：1998-08-21

申请人： Scott Pirdy ,  Allan Scott Baucom ,  Richard Hennessy ,  Scott Giordano ,  Sergio Parise

发明人： Scott Pirdy ,  Allan Scott Baucom ,  Richard Hennessy ,  Scott Giordano ,  Sergio Parise

IPC分类号： G06F1/16 ,  H05K5/00 ,  G06F12/00

CPC分类号： G06F1/1632

摘要： A docking system, including a portable computer and a docking unit, operates by latching the portable computer to the docking unit. A docking bay arrangement is used so that the portable computer's keyboard is accessible and usable by the user. A latch control system, which is controlled from the portable computer, provides security by preventing removal of the portable computer from the docking unit by unauthorized persons. This prevents theft, since the docking unit in turn is secured to the work area by a cable system.

摘要翻译： 包括便携式计算机和对接单元的对接系统通过将便携式计算机锁定到对接单元来操作。 使用对接托架布置，使得便携式计算机的键盘可由用户访问和使用。 由便携式计算机控制的闩锁控制系统通过防止未经授权的人员将便携式计算机从对接单元移除而提供安全性。 这防止盗窃，因为对接单元依次通过电缆系统固定到工作区域。