公开(公告)号：US20020143839A1

公开(公告)日：2002-10-03

申请号：US10016902

申请日：2001-12-14

申请人： Compaq Computer Corporation

发明人： Mark D. Matson ,  Robert J. Dupcak ,  Jonathan D. Krause ,  Sridhar Samudrala

IPC分类号： G06F007/38

CPC分类号： G06F7/535 ,  G06F7/4824 ,  G06F7/508 ,  G06F7/5525 ,  G06F9/3814 ,  G06F9/3838 ,  G06F9/384 ,  G06F2207/5352

摘要： The invention provides computer apparatus for performing a square root or division operation generating a root or quotient. A partial remainder is stored in radix-2 or radix-4 signed digit format. A decoder is provided for computing a root or quotient digit, and a correction term dependent on a number of the most significant digits of the partial remainder. An adder is provided for computing the sum of the signed digit partial remainder and the correction term in binary format, and providing the result in signed digit format. The adder computes a carry out independent of a carry in bit and a sum dependent on a Carry_in bit providing a fast adder independent of carry propagate delays. The scaler performs a multiplication by two of the result output from the adder in signed digit format to provide a signed digit next partial remainder.