公开(公告)号：US12131155B2

公开(公告)日：2024-10-29

申请号：US17597134

申请日：2020-03-25

申请人： ARM LIMITED ,  THE CHANCELLOR, MASTERS AND SCHOLARS OF THE UNIVERSITY OF CAMBRIDGE

发明人： Peng Sun ,  Timothy Martin Jones ,  Giacomo Gabrielli

IPC分类号： G06F9/30 ,  G06F9/345 ,  G06F9/355 ,  G06F9/38

CPC分类号： G06F9/30036 ,  G06F9/3004 ,  G06F9/3555 ,  G06F9/3842

摘要： An apparatus and method are provided for speculatively vectorising program code. The apparatus includes processing circuitry for executing program code, the program code including an identified code region comprising at least a plurality of speculative vector memory access instructions. Execution of each speculative vector memory access instruction is employed to perform speculative vectorisation of a series of scalar memory access operations using a plurality of lanes of processing. Tracking storage is used to maintain, for each speculative vector memory access instruction, tracking information providing an indication of a memory address being accessed within each lane. Checking circuitry then references the tracking information during execution of the identified code region by the processing circuitry, in order to detect any inter lane memory hazard resulting from the execution of the plurality of speculative vector memory access instructions.

公开(公告)号：US12124711B2

公开(公告)日：2024-10-22

申请号：US17944553

申请日：2022-09-14

申请人： Arm Limited

发明人： Roberto Avanzi

IPC分类号： G06F3/06

CPC分类号： G06F3/0623 ,  G06F3/0659 ,  G06F3/0673

摘要： Apparatus, methods, and software for protecting a plurality of memory locations are disclosed. Logical addresses are translated into physical addresses in dependence on one of a first translation function and a second translation function. A transitional logical address and an associated transitional value are locally held in circuitry which applies the translation functions. A remapping of first to second translation function usage is performed by determining a new transitional physical address by applying the second translation function to the transitional logical address; determining a new transitional logical address by applying an inverse of the first translation function to the new transitional physical address; retrieving a new transitional value using the new transitional physical address; storing the old transitional value to the memory location indicated by the new transitional physical address; and locally storing the new transitional value. This remapping can be interleaved with normal memory accesses.

公开(公告)号：US20240346155A1

公开(公告)日：2024-10-17

申请号：US18299216

申请日：2023-04-12

申请人： Arm Limited

发明人： Roberto AVANZI ,  Andreas Lars SANDBERG ,  Ionut Alexandru MIHALCEA ,  David Helmut SCHALL ,  Alexander KLIMOV

IPC分类号： G06F21/60 ,  G06F21/78

CPC分类号： G06F21/602 ,  G06F21/78

摘要： Apparatuses and methods for memory protection are disclosed. A memory protection apparatus is interposed between a system cache and a memory system. The apparatus comprises encryption circuitry, which encrypts data item in dependence on encryption metadata and decrypts encrypted data items in dependence on the encryption metadata. In response to a change in a metadata item of the encryption metadata, when no cached copy of an affected data item is currently in the system cache, the affected data item is retrieved from the memory system, re-encrypted using the updated metadata item and returned to the memory system. When there is a cached copy, in dependence on update control data, the copy is retrieved from the system cache, encrypted using the updated metadata item and written out to the memory system.

公开(公告)号：US12118101B2

公开(公告)日：2024-10-15

申请号：US17903267

申请日：2022-09-06

申请人： Arm Limited

发明人： Brendan James Moran ,  Adrian Laurence Shaw ,  Andreas Lars Sandberg

IPC分类号： G06F21/60 ,  G06F21/53

CPC分类号： G06F21/604 ,  G06F21/53

摘要： An apparatus and method are described for providing a trusted execution environment. The apparatus comprises processing circuitry to execute program code, and interrupt controller circuitry, responsive to receipt of one or more interrupt requests, to select a given interrupt request from amongst the one or more interrupt requests, and to issue an interrupt signal to the processing circuitry identifying a given interrupt service routine providing program code to be executed by the processing circuitry to service the given interrupt request. The interrupt controller circuitry is responsive to the given interrupt request being a trusted execution environment (TEE) interrupt request, to issue the interrupt signal to identify as the given interrupt service routine a TEE interrupt service routine, and to inhibit issuance of any further interrupt signal until the TEE interrupt service routine has been executed by the processing circuitry. The interrupt controller circuitry comprises code protection circuitry to inhibit unauthorised modification of the TEE interrupt service routine, and data protection circuitry to inhibit unauthorised access to confidential data processed by the TEE interrupt service routine.

公开(公告)号：US20240320332A1

公开(公告)日：2024-09-26

申请号：US18186454

申请日：2023-03-20

申请人： Arm Limited

发明人： Michael BARTLING

IPC分类号： G06F21/56 ,  G06F21/53

CPC分类号： G06F21/563 ,  G06F21/53

摘要： A live attack shadow replay can be performed at a shadow replay box that receives a snapshot of a computer program executed by an operating system of a device; mirrors an execution environment of the snapshot; determines a typical execution of the computer program comprising a first set of variables; performs a static analysis on the snapshot of the computer program to determine a second set of variables; determines a divergence between the first set of variables and the second set of variables; marks variables of the second set of variables that are associated with the divergence; replays a portion of the computer program corresponding to at least the snapshot; and monitors the marked variables of the second set of variables during the replaying of the portion of the computer program.

公开(公告)号：US20240320005A1

公开(公告)日：2024-09-26

申请号：US18125416

申请日：2023-03-23

申请人： Arm Limited

发明人： Jesse Garrett BEU ,  Thomas Christopher GROCUTT

IPC分类号： G06F9/30

CPC分类号： G06F9/30145 ,  G06F9/3001 ,  G06F9/30098

摘要： A data processing apparatus includes first vector registers and second vector registers, both dynamically spatially and dynamically temporally dividable. Decode circuitry receives one or more matrix multiplication instructions that indicate a set of first elements in the first vector registers and a set of second elements in the second vector registers, and in response to receiving the matrix multiplication instructions they generate a matrix multiplication operation. The matrix multiplication operation causes one or more execution units to perform a matrix multiplication of the set of first elements by the set of second elements and an average bit width of the first elements is different to an average bit width of the second elements.

公开(公告)号：US12099593B2

公开(公告)日：2024-09-24

申请号：US17245371

申请日：2021-04-30

申请人： Arm Limited

发明人： Oded Golombek ,  Einat Luko

IPC分类号： G06F21/00 ,  G06F21/44 ,  G06F21/62

CPC分类号： G06F21/44 ,  G06F21/6209

摘要： A method for authenticating an integrated circuit is provided. At an intellectual property facility, a random encryption key and a number of random input vectors are generated. For each input vector, the input vector is encrypted, based on the encryption key, to generate a corresponding output vector, and the input vector and the corresponding output vector are formed into an authentication vector pair. The encryption key is embedded into hardware description language instructions that define an integrated circuit that includes a cryptography engine. A number of authentication vector pairs is transmitted, via a secure communication link, to a semiconductor assembly and test facility. An input vector of an authentication vector pair is presented to the integrated circuit, which encrypts the input vector using the embedded encryption key. If the result matches the output vector of the authentication vector pair, the integrated circuit is determined to be authentic.

公开(公告)号：US12099447B2

公开(公告)日：2024-09-24

申请号：US17965173

申请日：2022-10-13

申请人： Arm Limited

发明人： Alexander Alfred Hornung ,  Roberto Gattuso

IPC分类号： G06F12/0862 ,  G06F12/0811 ,  G06F12/0871

CPC分类号： G06F12/0862 ,  G06F12/0811 ,  G06F12/0871

摘要： Prefetch circuitry generates, based on stream prefetch state information, prefetch requests for prefetching data to at least one cache. Cache control circuitry controls, based on cache policy information associated with cache entries in a given level of cache, at least one of cache entry replacement in the given level of cache, and allocation of data evicted from the given level of cache to a further level of cache. The stream prefetch state information specifies, for at least one stream of addresses, information representing an address access pattern for generating addresses to be specified by a corresponding series of prefetch requests. Cache policy information for at least one prefetched cache entry of the given level of cache (to which data is prefetched for a given stream of addresses) is set to a value dependent on at least one stream property associated with the given stream of addresses.

公开(公告)号：US20240311947A1

公开(公告)日：2024-09-19

申请号：US18184212

申请日：2023-03-15

申请人： Arm Limited

发明人： Rune HOLM ,  Elliot Maurice Simon ROSEMARINE

IPC分类号： G06T1/20 ,  G06T1/60

CPC分类号： G06T1/20 ,  G06T1/60

摘要： A processor, method and non-transitory computer-readable storage medium for handling data, by obtaining task data describing a task to be executed in the form of a plurality of operations on data, the task data further defining an operation space of said data, analyzing each of the operations to define transformation data comprising transformation instruction representing a transform into an associated operation-specific local spaces. In case transformation instructions to get to the operation-specific local space for an operation are producing less dimensions compared to the operation space, one or more operation-specific arguments are stored in a data field corresponding to a dimension not produced by the transformation instructions in the transformation data corresponding to the operation.

公开(公告)号：US20240302986A1

公开(公告)日：2024-09-12

申请号：US18664586

申请日：2024-05-15

申请人： Arm Limited

发明人： Seow Chuan LIM ,  Steven Douglas KRUEGER

IPC分类号： G06F3/06

CPC分类号： G06F3/0644 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0659 ,  G06F3/0673

摘要： An apparatus includes processing circuitry that performs data processing in response to instructions of a software execution environment. Configuration storage circuitry stores a set of memory transaction parameters in association with a partition identifier, and configuration application circuitry applies the set of memory transaction parameters with respect to memory transactions issued by the software execution environment that identifies the partition identifier. The memory transaction parameters comprise a minimum target allocation and a maximum target allocation of a storage capacity of at least part of a memory system in handling the memory transaction that identifies the partition identifier.