公开(公告)号：US20200265110A1

公开(公告)日：2020-08-20

申请号：US16280961

申请日：2019-02-20

申请人： Rohde & Schwarz GmbH & Co., KG

发明人： Luke Cirillo ,  Prabaker Balasubramanium

IPC分类号： G06F17/18 ,  G06N7/00 ,  G01R31/3183 ,  G06F9/54

摘要： A measurement system includes a measurement module, a processing module, and a display. The measurement module is configured to conduct measurements on a device under test in a repetitive manner in order to obtain measurement results assigned to the repeated measurements. The processing module is configured to combine the measurement results obtained. The processing module is also configured to perform a statistical analysis in a live manner in order to calculate at least one of a live statistical significance parameter of the combined measurement results and a time duration required to obtain a certain statistical significance of the measurement results. The display is configured to display at least one of the live statistical significance parameter and the time duration. Further, a method of providing statistical information is described.

公开(公告)号：US10739401B2

公开(公告)日：2020-08-11

申请号：US16017188

申请日：2018-06-25

申请人： International Business Machines Corporation

发明人： Satya R. S. Bhamidipati ,  Raghu G. Gopalakrishnasetty ,  Mary P. Kusko ,  Cedric Lichtenau

IPC分类号： G01R31/28 ,  G01R31/3177 ,  G01R31/317 ,  G01R31/3183 ,  G01R31/3185 ,  G01R31/3187

摘要： Aspects include a system having logic built-in self-test (LBIST) circuitry for use in an integrated circuit with scan chains. The system includes a pattern generator configured for generating scan-in test values for said scan chains; a signature register configured for collecting scan-out responses from said scan chains after a clock sequence; an on-product control generator configured for controlling at least one test parameter; one or more microcode array or memory elements configured to receive inputs to initialize fields in the microcode array or memory elements; and a test controller. The test controller includes a reader component configured for reading test parameters from a field of the microcode array or the memory elements; and a programming component configured for configuring the on-product control generator and the pattern generator with a LBIST pattern according to the read test parameters.

公开(公告)号：US20200158782A1

公开(公告)日：2020-05-21

申请号：US16398972

申请日：2019-04-30

申请人： International Business Machines Corporation

发明人： Pradip Bose ,  Alper Buyuktosunoglu ,  Schuyler Eldridge ,  Karthik V. Swaminathan ,  Yazhou Zu

IPC分类号： G01R31/3183 ,  G01R31/317 ,  G06F30/00

摘要： Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.

公开(公告)号：US10649031B2

公开(公告)日：2020-05-12

申请号：US15874287

申请日：2018-01-18

申请人： International Business Machines Corporation

发明人： Jeremy T. Ekman ,  Donald J. Ziebarth ,  George R. Zettles, IV ,  Trevor J. Timpane

IPC分类号： G01R31/3183 ,  G06F11/26 ,  G06F11/22 ,  H04L1/00 ,  G06F13/38 ,  G06F13/10 ,  H04L1/18 ,  H04L29/08 ,  G01R31/317 ,  H04L12/26

摘要： Hardware assisted high speed serial (HSS) transceiver testing including receiving, by a link layer hardware state machine on a HSS transmitting device, an instruction to generate a test pattern, wherein the test pattern comprises a sequence of data units; loading, by the link layer hardware state machine, each unique data unit into embedded random access memory (RAM); generating, by the link layer hardware state machine, the test pattern comprising the sequence of data units using the unique data units stored in the embedded RAM, wherein at least one of the unique data units is repeated in the sequence of data units of the test pattern; and sending, by the link layer hardware state machine, the generated test pattern to an input of a HSS transceiver.

公开(公告)号：US10598722B1

公开(公告)日：2020-03-24

申请号：US15784257

申请日：2017-10-16

申请人： Advanced Testing Technologies, Inc.

发明人： Robert Spinner ,  Eli Levi ,  Jim McKenna ,  William Harold Leippe ,  William Biagiotti ,  Richard Engel

IPC分类号： G01R31/28 ,  G01R31/3183 ,  G01R1/04

摘要： A mixed signal testing system capable of testing differently configured units under test (UUT) includes a controller, a test station and an interface system that support multiple UUTs. The test station includes independent sets of channels configured to send signals to and receive signals from each UUT being tested and signal processing subsystems that direct stimulus signals to a respective set of channels and receive signals in response thereto. The signal processing subsystems enable simultaneous and independent directing of stimulus signals through the sets of channels to each UUT and reception of signals from each UUT in response to the stimulus signals. Received signals responsive to stimulus signals provided to a fully functional UUT (with and without induced faults) are used to assess presence or absence of faults in the UUT being tested which may be determined to include one or more faults or be fault-free, i.e., fully functional.

公开(公告)号：US20200081039A1

公开(公告)日：2020-03-12

申请号：US16611337

申请日：2018-05-17

申请人： Byung Kyu KIM

发明人： Byung Kyu KIM ,  Byeong Yun KIM

IPC分类号： G01R19/00 ,  G01R31/3183 ,  G01R31/01 ,  G01R31/02 ,  G01R1/36

摘要： A current measurement apparatus comprises: a capacitor connected in parallel to a signal terminal of a device under test (DUT); a test pattern generation apparatus generating a test pattern to operate the DUT; and a measurement module connected to one end of the capacitor. The measurement module comprises: an input/output (I/O) buffer increasing or reducing an amount of charges of the capacitor and outputting a signal corresponding to an output logic value according to a voltage of the one end of the capacitor; a time measurer measuring an arrival time which it takes for the voltage of the one end of the capacitor to reach a second voltage from a first voltage; and a controller controlling the i/o buffer and the time measurer to measure the arrival time and controlling such that a value of a current related to an inspection of a DUT is measured using the arrival time.

公开(公告)号：US10585142B2

公开(公告)日：2020-03-10

申请号：US15718271

申请日：2017-09-28

申请人： International Business Machines Corporation

发明人： Mary P. Kusko ,  Franco Motika ,  Gerard M. Salem

IPC分类号： G01R31/317 ,  G01R31/3177 ,  G01R31/3183

摘要： An embodiment of the present invention provides a computer-implemented method for functional test and diagnostics of integrated circuits. The computer-implemented method includes executing one or more functional test exercisers in a functional execution sequence for a device under test up to one or more checkpoints, applying dynamic clock switching to a clock of the device under test to identify one or more likely causes of a failure identified at the one or more checkpoints, and includes iteratively invoking a portion of the functional execution sequence between a plurality of the checkpoints to progressively isolate the one or more likely causes of the failure as a most likely failure source based at least in part on the applied dynamic clock switching.

公开(公告)号：US20200041547A1

公开(公告)日：2020-02-06

申请号：US16595635

申请日：2019-10-08

申请人： Renesas Electronics Corporation

发明人： Kazuki FUKUOKA ,  Toshifumi UEMURA ,  Yuko KITAJI ,  Yosuke OKAZAKI ,  Akira MURAYAMA

IPC分类号： G01R19/165 ,  G01R31/28 ,  G06F1/28 ,  H03K5/133 ,  H03K3/03 ,  G06F1/24 ,  G01R31/317 ,  G01R31/3177 ,  G01R31/3183 ,  G01R31/3193

摘要： A semiconductor device, a semiconductor system, and a control method of a semiconductor device are capable of accurately monitoring the lowest operating voltage of a circuit to be monitored. According to one embodiment, a monitor unit of a semiconductor system includes a voltage monitor that is driven by a second power supply voltage different from a first power supply voltage supplied to an internal circuit that is a circuit to be monitored and monitors the first power supply voltage, and a delay monitor that is driven by the first power supply voltage and monitors the signal propagation period of time of a critical path in the internal circuit.

公开(公告)号：US10545190B2

公开(公告)日：2020-01-28

申请号：US15806388

申请日：2017-11-08

申请人： International Business Machines Corporation

发明人： Raghu G. GopalaKrishnaSetty ,  Mary P. Kusko ,  Spencer K. Millican

IPC分类号： G01R31/28 ,  G01R31/3183 ,  G06F17/50 ,  G01R31/3185

摘要： Embodiments include techniques for using circuit structures for resolving random testability, the techniques includes analyzing a logic structures of a circuit design, and identifying the logic structures of the circuit that are random resistant structures. The techniques also include replacing the logic structures with random testable structures, and performing a test of the circuit design.

公开(公告)号：US10545187B2

公开(公告)日：2020-01-28

申请号：US16284465

申请日：2019-02-25

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Lee D. Whetsel

IPC分类号： G01R31/317 ,  G01R31/3177 ,  G01R31/3185 ,  G01R31/28 ,  G01R31/3183

摘要： This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.