-
公开(公告)号：US09317353B2
公开(公告)日：2016-04-19
申请号：US14140834
申请日：2013-12-26
申请人： Intel Corporation
发明人： Sanjay R. Ravi
CPC分类号： G06F11/076 , G01R31/3004 , G06F11/0745 , H04L25/4923
摘要： In one embodiment, a receiver is coupled to a transmitter via an interconnect. The receiver includes a voltage margining circuit to receive non-deterministic data transmitted by the transmitter via a multi-level signaling scheme and to generate a bit error report including bit error information obtained at a plurality of margining levels. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，接收器经由互连耦合到发射器。 接收机包括电压余量电路，用于经由多电平信令方案接收由发射机发送的非确定性数据，并产生包括在多个边缘级别获得的位错误信息的位错误报告。 描述和要求保护其他实施例。
-
82.发明授权公开(公告)号：US09300513B2
公开(公告)日：2016-03-29
申请号：US14595653
申请日：2015-01-13
发明人： Seunghyun Jang , Young Kyun Cho , Sung Jun Lee , Bong Hyuk Park , Jae Ho Jung , Kwangchun Lee
CPC分类号： H04L27/2627 , H03F1/3247 , H03F3/24 , H04L25/4902 , H04L25/4923 , H04L27/20 , H04L27/368
摘要： Provided is a signal transmission device including a first modulation unit generating a first modulated signal having at least three logic levels by modulating an input signal; a characteristic adjustment unit generating an adjusted first modulated signal by adjusting the at least one of electrical characteristic values based on an adjustment signal; a second modulation unit generating a second modulated signal by modulating the adjusted first modulated signal; and an adjustment operation unit generating the adjustment signal based on electrical characteristic values respectively corresponding to the at least three logic levels of the first modulated signal and corresponding to at least three logic levels of the second modulated signal. Linearity of the modulated signal generated by the provided signal transmission device is enhanced.
摘要翻译： 提供了一种信号传输设备，包括：第一调制单元，通过调制输入信号产生具有至少三个逻辑电平的第一调制信号; 特征调整单元，通过基于调整信号调整所述电特性值中的至少一个来生成经调整的第一调制信号; 第二调制单元，通过调制经调整的第一调制信号产生第二调制信号; 以及调整操作单元，其基于分别对应于所述第一调制信号的所述至少三个逻辑电平并对应于所述第二调制信号的至少三个逻辑电平的电特性值生成所述调整信号。 由提供的信号传输装置产生的调制信号的线性增强。
-
公开(公告)号：US09178690B2
公开(公告)日：2015-11-03
申请号：US14252450
申请日：2014-04-14
发明人： Shoichiro Sengoku
CPC分类号： H04L7/0337 , H04L5/0053 , H04L7/0012 , H04L7/0087 , H04L7/033 , H04L25/14 , H04L25/49 , H04L25/4923
摘要： System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. Each symbol in a sequence of symbols received from a plurality of signal wires is received in an odd transmission interval or an even transmission interval. A first clock signal is generated from transitions in signaling state of the wires occurring between each odd transmission interval and a consecutive even transmission interval. A second clock signal is generated from transitions in signaling state of the plurality of wires occurring between each even transmission interval and a consecutive odd transmission interval. The first and second clock signals are used to capture symbols received in even and odd transmission intervals, respectively.
摘要翻译： 描述了便于通过多线数据通信链路，特别是在电子设备内的两个设备之间传输数据的系统，方法和装置。 在多个信号线中接收的符号序列中的每个符号以奇数传输间隔或偶数传输间隔被接收。 在每个奇数传输间隔和连续偶数传输间隔之间发生的布线的信令状态的转换产生第一时钟信号。 第二时钟信号由在每个偶数传输间隔和连续的奇数传输间隔之间发生的多条线的信令状态的转换产生。 第一和第二时钟信号分别用于捕获在偶数和奇数传输间隔中接收的符号。
-
84.发明授权公开(公告)号：US09143306B2
公开(公告)日：2015-09-22
申请号：US13272060
申请日：2011-10-12
CPC分类号： A43C11/165 , H04L5/1423 , H04L25/4908 , H04L25/4923 , Y10T24/2183
摘要： A device and method for encoding bits to symbols for a communication system are described. In one embodiment, a method for encoding bits to symbols for a communication system includes receiving a set of N-bit data to be transmitted, where N is an integer, generating side scrambling values using a polynomial, scrambling the set of N-bit data using the side scrambling values to produce scrambled data, mapping the scrambled data to a particular set of M symbols from a plurality of sets of M symbols, where M is an integer and M is smaller than N, and outputting the particular set of M symbols for transmission over a transmission medium. Other embodiments are also described.
摘要翻译： 描述用于将位编码到用于通信系统的符号的装置和方法。 在一个实施例中，用于将比特编码为用于通信系统的符号的方法包括：接收要发送的一组N比特数据，其中N是整数，使用多项式生成侧加扰值，对该N比特数据集进行加扰 使用侧扰频值产生加扰数据，将加扰数据映射到多个M个符号集合中的M个符号的特定集合，其中M是整数并且M小于N，并且输出特定的一组M个符号 用于在传输介质上传输。 还描述了其它实施例。
-
公开(公告)号：US20150098536A1
公开(公告)日：2015-04-09
申请号：US14252450
申请日：2014-04-14
发明人： Shoichiro Sengoku
CPC分类号： H04L7/0337 , H04L5/0053 , H04L7/0012 , H04L7/0087 , H04L7/033 , H04L25/14 , H04L25/49 , H04L25/4923
摘要： System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. Each symbol in a sequence of symbols received from a plurality of signal wires is received in an odd transmission interval or an even transmission interval. A first clock signal is generated from transitions in signaling state of the wires occurring between each odd transmission interval and a consecutive even transmission interval. A second clock signal is generated from transitions in signaling state of the plurality of wires occurring between each even transmission interval and a consecutive odd transmission interval. The first and second clock signals are used to capture symbols received in even and odd transmission intervals, respectively.
摘要翻译： 描述了便于通过多线数据通信链路，特别是在电子设备内的两个设备之间传输数据的系统，方法和装置。 在多个信号线中接收的符号序列中的每个符号以奇数传输间隔或偶数传输间隔被接收。 在每个奇数传输间隔和连续偶数传输间隔之间发生的布线的信令状态的转换产生第一时钟信号。 第二时钟信号由在每个偶数传输间隔和连续的奇数传输间隔之间发生的多条线的信令状态的转换产生。 第一和第二时钟信号分别用于捕获在偶数和奇数传输间隔中接收的符号。
-
86.发明申请TERNARY SEQUENCES WITH POWER OF TWO EXPONENT DIMENSIONALITIES SUITABLE FOR CHANNEL ESTIMATION 有权具有适用于信道估计的两个指标尺寸的三次序列公开(公告)号：US20150098345A1
公开(公告)日：2015-04-09
申请号：US14049256
申请日：2013-10-09
发明人： Siavash Ekbatani , Alok Kumar Gupta
CPC分类号： H04L25/024 , G01S5/00 , G01S5/0205 , G01S5/0215 , G01S5/0221 , G01S5/0226 , G01S5/06 , G01S11/08 , G06Q10/00 , G08B21/0272 , H04L25/0226 , H04L25/4923 , H04W64/00
摘要： Methods, systems, and devices for channel estimation in a location tracking system are described. The methods, system, and devices may include tools and techniques for determining and/or designing perfect or semi-perfect sequences (including preamble sequences) for implementation in a location tracking system. Sequences having 2's exponent dimensionality, such as ternary sequences, may be determined and employed, which may help reduce implementation complexity and/or operating power consumption. Sequences may be determined using mean square error and/or maximum autocorrelation peak performance metrics.
摘要翻译： 描述了位置跟踪系统中用于信道估计的方法，系统和设备。 方法，系统和装置可以包括用于确定和/或设计用于在位置跟踪系统中实现的完美或半完美序列（包括前导码序列）的工具和技术。 可以确定并采用具有2个指数维数的序列，例如三进制序列，这有助于降低实现复杂度和/或操作功耗。 序列可以使用均方误差和/或最大自相关峰性能度量来确定。
-
公开(公告)号：US20140006649A1
公开(公告)日：2014-01-02
申请号：US13895651
申请日：2013-05-16
发明人： George A. Wiley , Glenn D. Raskin , Chulkyu Lee
IPC分类号： G06F13/38
CPC分类号： H04L25/02 , G06F13/385 , H04L5/1423 , H04L5/16 , H04L25/0272 , H04L25/14 , H04L25/4923 , H04L25/493
摘要： System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Data is selectively transmitted as N-phase polarity encoded symbols or as packets on differentially driven connectors. A desired operational mode for communicating between the two devices is determined, an encoder is selected to drive a plurality of connectors communicatively coupling the two devices, and a plurality of drivers is configured to receive encoded data from the encoder and drive the plurality of connectors. Switches may couple outputs of the selected encoder to the plurality of drivers. One or more outputs of another encoder may be caused or forced to enter a high impedance mode.
摘要翻译： 描述了促进数据传输的系统，方法和装置，特别是在电子设备内的两个设备之间。 选择性地将数据作为N相极性编码的符号或作为差分驱动的连接器上的分组发送。 确定用于在两个设备之间通信的期望的操作模式，选择编码器来驱动通信地耦合两个设备的多个连接器，并且多个驱动器被配置为从编码器接收编码数据并驱动多个连接器。 开关可以将所选择的编码器的输出耦合到多个驱动器。 可能引起另一个编码器的一个或多个输出或强制进入高阻抗模式。
-
公开(公告)号：US08436653B2
公开(公告)日：2013-05-07
申请号：US13227319
申请日：2011-09-07
申请人： Timothy M. Hollis
发明人： Timothy M. Hollis
IPC分类号： H03K19/00
CPC分类号： H04L25/4917 , H03K19/0002 , H04L25/4923 , H04L25/4927
摘要： Apparatus are disclosed, such as those involving a transmitter circuit that is configured to generate multi-level signals based on a plurality of data digits. One such transmitter circuit includes a signal output and an encoder configured to provide control signals based at least partially on the plurality of data digits. The transmitter circuit also includes a first set of switches configured to receive one or more of the control signals, and to selectively conduct a first or second voltage reference to the signal output. The transmitter circuit further includes first and second voltage drop circuits that provide third and fourth voltage references, respectively. The third and fourth voltage references have voltage levels between those of the first and second voltage references. The transmitter circuit also includes a second set of switches configured to receive one or more of the control signals, and selectively conduct the third or fourth voltage reference to the signal output.
摘要翻译： 公开了诸如涉及发射机电路的装置，其被配置为基于多个数字数字产生多电平信号。 一个这样的发射机电路包括信号输出和被配置为至少部分地基于多个数字数字提供控制信号的编码器。 发射机电路还包括被配置为接收一个或多个控制信号的第一组开关，并且选择性地对信号输出进行第一或第二电压基准。 发射机电路还包括分别提供第三和第四电压参考的第一和第二电压降电路。 第三和第四参考电压具有在第一和第二参考电压之间的电压电平。 发射机电路还包括被配置为接收一个或多个控制信号的第二组开关，并且选择性地将第三或第四电压基准传送到信号输出端。
-
公开(公告)号：US08369443B2
公开(公告)日：2013-02-05
申请号：US13175906
申请日：2011-07-04
申请人： Isaac Y. Chen
发明人： Isaac Y. Chen
IPC分类号： H04L25/49
CPC分类号： H04L25/4923 , H04L5/04 , H04L7/044
摘要： The present invention discloses a single-wire asynchronous serial interface, and a method for transmitting commands and data through one transmission wire, wherein the transmission wire is capable of transmitting signals of three level states. The disclosed interface comprises a signal level extraction circuit receiving signals transmitted through the wire and outputting logic or functional bits according to the received signals; a clock extraction circuit generating clock signals according to the functional bits, and a memory circuit controlled by the clock signals and storing the logic bits. The disclosed method comprises: using two of the level states to represent logic 0 and logic 1, and the third of the states as a functional bit; and determining whether a group of signals is a command or data by the existence of a functional bit within the group.
摘要翻译： 本发明公开了一种单线异步串行接口，以及一种通过一条传输线传输命令和数据的方法，其中传输线能传输三电平状态信号。 所公开的接口包括：信号电平提取电路，接收通过线路传输的信号，并根据接收到的信号输出逻辑或功能位; 根据功能位产生时钟信号的时钟提取电路和由时钟信号控制并存储逻辑比特的存储器电路。 所公开的方法包括：使用两个电平状态来表示逻辑0和逻辑1，并且将第三个状态用作功能位; 以及通过所述组内的功能位的存在来确定一组信号是否是命令或数据。
-
90.发明授权公开(公告)号：US08189704B2
公开(公告)日：2012-05-29
申请号：US12359778
申请日：2009-01-26
IPC分类号： H04L5/12
CPC分类号： H04L25/4923 , H04L25/03229 , H04L2025/03363
摘要： A method and apparatus are provided for joint equalization and decoding of multilevel codes, such as the Multilevel Threshold-3 (MLT-3) code, which are transmitted over dispersive channels. The MLT-3 code is treated as a code generated by a finite-state machine using a trellis having state dependencies between the various states. A super trellis concatenates the MLT-3 trellis with a trellis representation of the channel. Joint equalization and decoding of the received signal can be performed using the super trellis. A sequence detector is disclosed that uses the super trellis or a corresponding reduced-state trellis to perform joint equalization and decoding of the received signal to decode the MLT-3 coded data bits. The sequence detector may be embodied using maximum likelihood sequence estimation that applies the optimum Viterbi algorithm or a reduced complexity sequence estimation method, such as the reduced-state sequence estimation (RSSE) algorithm.
摘要翻译： 提供了一种用于联合均衡和解码多级代码的方法和装置，例如在色散通道上传输的多级阈值-3（MLT-3）码。 MLT-3代码被视为由有限状态机使用在各种状态之间具有状态依赖性的网格生成的代码。 超级网格将MLT-3网格与网络格式的通道连接起来。 接收信号的联合均衡和解码可以使用超级格子进行。 公开了一种序列检测器，其使用超级格或相应的缩减状态网格来对接收到的信号进行联合均衡和解码，以解码MLT-3编码的数据位。 可以使用应用最优维特比算法或缩减复杂度序列估计方法（例如缩减状态序列估计（RSSE）算法）的最大似然序列估计来体现序列检测器。
-
-
-
-
-
-
-
-
-
搜索结果
193 条记录 (耗时 0.025 秒)
