公开(公告)号：US07746181B1

公开(公告)日：2010-06-29

申请号：US11329787

申请日：2006-01-10

Applicant: Nathan Moyal

Inventor： Nathan Moyal

IPC: H03L7/181 ,  G01R23/15

CPC classification number: H03L7/099 ,  H03L1/00 ,  H03L7/087 ,  H03L7/18

Abstract: An improved circuit and method is described herein for extending the usable frequency range of a high performance, narrow band phase locked loop (PLL) device. For example, the improved circuit and method may perform a calibration sequence for calibrating an LC-type voltage controlled oscillator (VCO) immediately before or during operation of the PLL device. Unlike previous methods, the calibration sequence described herein provides a fast and convenient method for extending the usable frequency range of a PLL by shifting the center frequency of the LC-type VCO to a desired frequency. For example, the VCO center frequency may be incrementally shifted (e.g., either high or low) to compensate for the actual environmental conditions in which the PLL is used (i.e., to compensate for specific process, voltage, and temperature conditions). Once the calibration bits are set to the desired frequency, the calibration sequence is disabled, and the appropriate calibration bit values are applied to the VCO during normal operation of the PLL.

Abstract translation: 本文描述了一种改进的电路和方法，用于扩展高性能窄带锁相环（PLL）装置的可用频率范围。 例如，改进的电路和方法可以在PLL器件之前或期间执行用于校准LC型压控振荡器（VCO）的校准序列。 与以前的方法不同，本文所述的校准序列提供了一种用于通过将LC型VCO的中心频率移动到期望频率来扩展PLL的可用频率范围的快速和方便的方法。 例如，VCO中心频率可以递增地移位（例如，高或低）以补偿使用PLL的实际环境条件（即，补偿特定过程，电压和温度条件）。 一旦校准位被设置为所需的频率，校准序列被禁用，并且在PLL的正常操作期间将适当的校准位值施加到VCO。

公开(公告)号：US07688151B2

公开(公告)日：2010-03-30

申请号：US12121081

申请日：2008-05-15

Applicant: Tung-Teh Lee

Inventor： Tung-Teh Lee

IPC: G01R23/00 ,  H03B5/32 ,  H03B5/36 ,  H03L7/085

CPC classification number: H03L1/00

Abstract: An aging compensation method for an oscillator circuit device, in which the oscillator circuit device receives a control voltage from an application end, and outputs a clock signal with a predetermined frequency in response to the control voltage, includes the steps of: a) inspecting the control voltage from the application end to obtain a first value thereof; b) after a predetermined time period has elapsed, inspecting the control voltage from the application end to obtain a second value thereof; c) determining whether there is a difference between the first and second values of the control voltage; d) if it is determined that there is a difference, performing compensation on the value of the control voltage based on the difference; and e) repeating steps b) through d).

Abstract translation: 振荡电路装置的老化补偿方法，其中振荡电路装置从应用端接收控制电压，并响应于控制电压输出具有预定频率的时钟信号，包括以下步骤：a）检查 控制电压从应用端获得其第一值; b）在经过预定时间段之后，检查来自应用端的控制电压以获得其第二值; c）确定控制电压的第一和第二值之间是否存在差异; d）如果确定存在差异，则根据差异对控制电压的值进行补偿; 和e）重复步骤b）至d）。

公开(公告)号：US07656243B2

公开(公告)日：2010-02-02

申请号：US10593354

申请日：2005-03-21

Applicant: Michael Shannon McCorquodale ,  Scott Michael Pernia ,  Amar Sarbbasesh Basu

Inventor： Michael Shannon McCorquodale ,  Scott Michael Pernia ,  Amar Sarbbasesh Basu

IPC: H03B5/12

CPC classification number: H03L1/02 ,  H03B5/04 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1253 ,  H03B5/1265 ,  H03B2200/0038 ,  H03B2200/005 ,  H03B2200/0098 ,  H03J2200/10 ,  H03L1/00 ,  H03L1/026 ,  H03L7/00 ,  H03L7/06 ,  H03L7/0812 ,  H03L7/099 ,  H03L7/24

Abstract: In various embodiments, the invention provides a clock generator and/or a timing and frequency reference, with multiple operating modes, such power conservation, clock, reference, and pulsed modes. The various apparatus embodiments include a resonator adapted to provide a first signal having a resonant frequency; an amplifier; a temperature compensator adapted to modify the resonant frequency in response to temperature; and a process variation compensator adapted to modify the resonant frequency in response to fabrication process variation. In addition, the various embodiments may also include a frequency divider adapted to divide the first signal having the resonant frequency into a plurality of second signals having a corresponding plurality of frequencies substantially equal to or lower than the resonant frequency; and a frequency selector adapted to provide an output signal from the plurality of second signals. The output signal may be provided in any of various forms, such as differential or single-ended, and substantially square-wave or sinusoidal.

Abstract translation: 在各种实施例中，本发明提供具有多种操作模式的时钟发生器和/或定时和频率参考，例如功率节省，时钟，参考和脉冲模式。 各种装置实施例包括适于提供具有谐振频率的第一信号的谐振器; 放大器 温度补偿器，其适于根据温度修改谐振频率; 以及适于响应于制造工艺变化来修改谐振频率的工艺变化补偿器。 此外，各种实施例还可以包括分频器，其适于将具有谐振频率的第一信号划分成具有基本上等于或低于谐振频率的相应多个频率的多个第二信号; 以及适于提供来自所述多个第二信号的输出信号的频率选择器。 输出信号可以以各种形式提供，例如差分或单端，以及基本方波或正弦。

公开(公告)号：US20100019856A1

公开(公告)日：2010-01-28

申请号：US12435269

申请日：2009-05-04

Applicant: Michael Shannon McCorquodale ,  Scott Michael Pernia ,  Amar Sarbbasesh Basu

Inventor： Michael Shannon McCorquodale ,  Scott Michael Pernia ,  Amar Sarbbasesh Basu

IPC: H03B5/12

CPC classification number: H03L1/02 ,  H03B5/04 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1253 ,  H03B5/1265 ,  H03B2200/0038 ,  H03B2200/005 ,  H03B2200/0098 ,  H03J2200/10 ,  H03L1/00 ,  H03L1/026 ,  H03L7/00 ,  H03L7/06 ,  H03L7/0812 ,  H03L7/099 ,  H03L7/24

Abstract: In various embodiments, the invention provides a clock generator and/or a timing and frequency reference, with multiple operating modes, such power conservation, clock, reference, and pulsed modes. The various apparatus embodiments include a resonator adapted to provide a first signal having a resonant frequency; an amplifier; a temperature compensator adapted to modify the resonant frequency in response to temperature; and a process variation compensator adapted to modify the resonant frequency in response to fabrication process variation. In addition, the various embodiments may also include a frequency divider adapted to divide the first signal having the resonant frequency into a plurality of second signals having a corresponding plurality of frequencies substantially equal to or lower than the resonant frequency; and a frequency selector adapted to provide an output signal from the plurality of second signals. The output signal may be provided in any of various forms, such as differential or single-ended, and substantially square-wave or sinusoidal.

Abstract translation: 在各种实施例中，本发明提供具有多种操作模式的时钟发生器和/或定时和频率参考，例如功率节省，时钟，参考和脉冲模式。 各种装置实施例包括适于提供具有谐振频率的第一信号的谐振器; 放大器 温度补偿器，其适于根据温度修改谐振频率; 以及适于响应于制造工艺变化来修改谐振频率的工艺变化补偿器。 此外，各种实施例还可以包括分频器，其适于将具有谐振频率的第一信号划分成具有基本上等于或低于谐振频率的相应多个频率的多个第二信号; 以及适于提供来自所述多个第二信号的输出信号的频率选择器。 输出信号可以以各种形式提供，例如差分或单端，以及基本方波或正弦。

公开(公告)号：US20090256639A1

公开(公告)日：2009-10-15

申请号：US12401501

申请日：2009-03-10

Applicant: Huan-Ke Chiu ,  Chun-Jen Chen

Inventor： Huan-Ke Chiu ,  Chun-Jen Chen

IPC: H03L7/00

CPC classification number: H03L7/107 ,  H03L1/00 ,  H03L7/099 ,  H03L2207/06 ,  H03L2207/50

Abstract: An all-digital phase-locked loop is disclosed. The all-digital phase-locked loop includes a digitally controlled oscillator, a phase detector, a loop filter, and a bandwidth modification unit. The digitally controlled oscillator is controlled by an oscillator tuning word to generate a variable signal, wherein the oscillator tuning word includes a first tuning word and a second tuning word respectively to adjust the capacitance of a first capacitor set and the capacitance of a second capacitor set. The phase detector measures a phase error between the variable signal and a reference signal. The loop filter receives the phase error to generate an initial tuning word. The bandwidth modification unit receives the initial tuning word to adjust the initial tuning word to generate the tuning word according to the available usage range of the first capacitor set and the second capacitor set.

Abstract translation: 公开了一种全数字锁相环。 全数字锁相环包括数字控制振荡器，相位检测器，环路滤波器和带宽修改单元。 数字控制振荡器由振荡器调谐字控制以产生可变信号，其中振荡器调谐字分别包括第一调谐字和第二调谐字，以调整第一电容器组的电容和第二电容器组的电容 。 相位检测器测量可变信号和参考信号之间的相位误差。 环路滤波器接收相位误差以产生初始调谐字。 带宽修改单元接收初始调谐字以根据第一电容器组和第二电容器组的可用使用范围调整初始调谐字以产生调谐字。

公开(公告)号：US07592877B2

公开(公告)日：2009-09-22

申请号：US11771403

申请日：2007-06-29

Applicant: Nobuhiro Shiramizu ,  Toru Masuda

Inventor： Nobuhiro Shiramizu ,  Toru Masuda

IPC: H03B5/24

CPC classification number: H03L7/0995 ,  H03K3/0322 ,  H03K3/35613 ,  H03K5/133 ,  H03K2005/00208 ,  H03K2005/00234 ,  H03L1/00 ,  H03L7/0891 ,  H03L7/18 ,  H03M9/00

Abstract: In a variable frequency oscillator in a semiconductor device, as the variation of an oscillation frequency caused by the variation of temperature and supply voltage and process variation is large, it is difficult to reduce the conversion ratio of control voltage dependent upon phase noise and the oscillation frequency and therefore, phase noise is large. The variation of the oscillation frequency is suppressed and phase noise is reduced by connecting a voltage-to-current conversion circuit that converts input control voltage to control current of a ring oscillator to the ring oscillator where delay circuits a delay time of which increases and decreases according to the amplitude of input control current are cascade-connected by a plurality of stages in a ring and increasing/decreasing current dependent upon any of temperature, supply voltage and the threshold voltage of a transistor inside the voltage-to-current conversion circuit.

Abstract translation: 在半导体器件的可变频率振荡器中，随着由温度和电源电压的变化引起的振荡频率的变化和工艺变化的变化大，难以根据相位噪声和振荡来降低控制电压的转换比 因此，相位噪声较大。 通过连接将输入控制电压转换为环形振荡器的控制电流的电压 - 电流转换电路，振荡频率的变化被抑制，并且相位噪声减小，其中延迟电路的延迟时间增加和减小 根据输入控制电流的幅度通过环中的多个级级联连接，并且取决于电压 - 电流转换电路内的晶体管的温度，电源电压和阈值电压中的任一个的增加/减少电流。

公开(公告)号：US20090231048A1

公开(公告)日：2009-09-17

申请号：US12073958

申请日：2008-03-12

Applicant: Ananda S. Natarajan ,  Jithin Janardhan

Inventor： Ananda S. Natarajan ,  Jithin Janardhan

IPC: H03K3/03

CPC classification number: H03K5/133 ,  H03K3/011 ,  H03K3/0322 ,  H03K2005/00123 ,  H03K2005/0013 ,  H03K2005/00143 ,  H03K2005/00202 ,  H03K2005/00208 ,  H03L1/00

Abstract: Bias circuits to stabilize oscillation in ring oscillators, oscillators, and methods to stabilize oscillation in ring oscillators are provided. The ring oscillator includes a plurality of differential delay cells, each including a pair of input transistors, a pair of voltage-controlled resistors, and a common current source. The bias circuit includes a replica arm that includes a replica of one of the voltage-controlled resistors, and a resistor arm that includes a fixed resistor. The bias circuit supplies bias voltages to the differential delay cells such that ratio of voltage swing to bias current of the delay cell is kept constant by referring the ratio to the fixed resistor.

Abstract translation: 提供了用于稳定环形振荡器中的振荡的偏置电路，振荡器和稳定环形振荡器中的振荡的方法。 环形振荡器包括多个差分延迟单元，每个差分延迟单元包括一对输入晶体管，一对压控电阻器和公共电流源。 偏置电路包括复制臂，其包括压控电阻器之一的副本，以及包括固定电阻器的电阻臂。 偏置电路向差分延迟单元提供偏置电压，使得延迟单元的电压摆幅与偏置电流的比率通过参考固定电阻器的比率而保持恒定。

公开(公告)号：US07583154B1

公开(公告)日：2009-09-01

申请号：US11241078

申请日：2005-09-30

Applicant: John Kizziar

Inventor： John Kizziar

IPC: H03L1/00

CPC classification number: H03L1/00 ,  H03B5/04 ,  H03B5/1243 ,  H03L7/099

Abstract: A voltage-controlled oscillator is provided that avoids use of any crystal resonator, or any resonator that is external to and not integrated upon the voltage-controlled oscillator monolithic substrate. The present oscillator can receive two or more parameters that would likely have an affect on the oscillator frequency, yet the oscillator includes compensating transfer functions that will remove, or correct for, that effect. Transfer functions involve electronic subsystems implemented in hardware or software that receive the input parameter that has changed from a nominal value, and will note the drift in output frequency, yet will compensate for that drift so that the output frequency remains near the nominal value. The voltage-controlled oscillator preferably is an LCVCO, and the transfer function outputs can be summed to take into account multiple parameter changes. In addition, the output frequency can be placed into a wider band spread spectrum output using a modulating, spread spectrum circuitry if desired.

Abstract translation: 提供了一种压控振荡器，其避免使用任何晶体谐振器，或者任何在压控振荡器单片基板上外部并未集成的谐振器。 本振荡器可以接收可能对振荡器频率产生影响的两个或更多个参数，但是振荡器包括将去除或校正该效应的补偿传递函数。 传输功能涉及以硬件或软件实现的电子子系统，其接收已经从标称值变化的输入参数，并且将注意到输出频率的漂移，而且将补偿该漂移，使得输出频率保持接近标称值。 压控振荡器优选地是LCVCO，并且传递函数输出可以相加以考虑多个参数改变。 此外，如果需要，可以使用调制扩频电路将输出频率放置在更宽的频带扩频输出中。

公开(公告)号：US07548132B2

公开(公告)日：2009-06-16

申请号：US11796821

申请日：2007-04-28

Applicant: Michael Shannon McCorquodale ,  Scott Michael Pernia ,  Amar Sarbbasesh Basu

Inventor： Michael Shannon McCorquodale ,  Scott Michael Pernia ,  Amar Sarbbasesh Basu

IPC: H03B5/12

CPC classification number: H03L1/02 ,  H03B5/04 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1253 ,  H03B5/1265 ,  H03B2200/0038 ,  H03B2200/005 ,  H03B2200/0098 ,  H03J2200/10 ,  H03L1/00 ,  H03L1/026 ,  H03L7/00 ,  H03L7/06 ,  H03L7/0812 ,  H03L7/099 ,  H03L7/24

Abstract: In various embodiments, the invention provides a clock generator and/or a timing and frequency reference, with multiple operating modes, such power conservation, clock, reference, and pulsed modes. The various apparatus embodiments include a resonator adapted to provide a first signal having a resonant frequency; an amplifier; a temperature compensator adapted to modify the resonant frequency in response to temperature; and a process variation compensator adapted to modify the resonant frequency in response to fabrication process variation. In addition, the various embodiments may also include a frequency divider adapted to divide the first signal having the resonant frequency into a plurality of second signals having a corresponding plurality of frequencies substantially equal to or lower than the resonant frequency; and a frequency selector adapted to provide an output signal from the plurality of second signals. The output signal may be provided in any of various forms, such as differential or single-ended, and substantially square-wave or sinusoidal.

Abstract translation: 在各种实施例中，本发明提供具有多种操作模式的时钟发生器和/或定时和频率参考，例如功率节省，时钟，参考和脉冲模式。 各种装置实施例包括适于提供具有谐振频率的第一信号的谐振器; 放大器 温度补偿器，其适于根据温度修改谐振频率; 以及适于响应于制造工艺变化来修改谐振频率的工艺变化补偿器。 此外，各种实施例还可以包括分频器，其适于将具有谐振频率的第一信号划分成具有基本上等于或低于谐振频率的相应多个频率的多个第二信号; 以及适于提供来自所述多个第二信号的输出信号的频率选择器。 输出信号可以以各种形式提供，例如差分或单端，以及基本方波或正弦。

公开(公告)号：US07548131B2

公开(公告)日：2009-06-16

申请号：US11754409

申请日：2007-05-29

Applicant: Mineo Noguchi

Inventor： Mineo Noguchi

IPC: H03K3/0231

CPC classification number: H03L1/00 ,  H03K3/011 ,  H03K3/03

Abstract: An output signal ZA of NAND 48a is given to a first input of NAND 48b and is given to a second input of the above NAND 48b, simultaneously through a delay circuit. Furthermore, an output signal ZB of the NAND 48b is given to the first input of NAND 48a and is given to the second input of NAND 48a, simultaneously through a delay circuit. The delay circuit includes a charging and discharging circuit consisting of a NMOS 42 having the conductivity controlled by a voltage VN depending on a temperature signal from a temperature-dependent current source 30 and a capacitor 44, and a NMOS 45 being turned on/off by the voltage of the above capacitor 44. By setting temperature characteristics of the voltage VN and temperature characteristics of the threshold voltage of the NMOS 45 so as to cancel each other, the oscillation frequency variation of the oscillation circuit consisting of astable multi-vibrators can be restrained.

Abstract translation: NAND 48a的输出信号ZA被提供给NAND48b的第一输入，并且通过延迟电路同时被提供给上述NAND48b的第二输入。 此外，NAND48b的输出信号ZB被提供给NAND 48a的第一输入，并且通过延迟电路同时被提供给NAND 48a的第二输入。 延迟电路包括充电和放电电路，该充电和放电电路由具有由依赖于温度的电流源30和电容器44的温度信号的电压VN控制的电导率的NMOS42和NMOS45通过 上述电容器44的电压。通过设定电压VN的温度特性和NMOS45的阈值电压的温度特性彼此抵消，由可振荡的多个振动器组成的振荡电路的振荡频率变化可以是 束缚