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公开(公告)号：US20150109043A1
公开(公告)日：2015-04-23
申请号：US14058428
申请日：2013-10-21
发明人： Alan James Drake , Michael Stephen Floyd , Pawel Owczarczyk , Gregory Scott Still , Marshall Dale Tiner , Xiaobin Yuan
IPC分类号： H03K5/159
CPC分类号： H03K5/159
摘要： A critical path monitor (CPM) having a set of split paths is configured in an integrated circuit (IC) that includes a corresponding set of critical paths. A first and a second split path is configured with a first and a second simulated delay sections and fine delay sections, respectively. A delay of each of the first and second fine delay sections is adjustable in several steps. The delay of the first fine delay section is adjustable differently from the delay of the second fine delay section in response to a common operating condition change. Differently adjusting the delays of the first and the second fine delay sections causes an edge of a pulse to be synchronized between a first edge detector located after the first simulated delay section and a second edge detector located after the second simulated delay section.
摘要翻译： 具有一组分离路径的关键路径监视器（CPM）被配置在包括相应的一组关键路径的集成电路（IC）中。 第一和第二分割路径分别配置有第一和第二模拟延迟部分和精细延迟部分。 第一和第二精细延迟部分中的每一个的延迟可以在几个步骤中调节。 响应于共同的操作条件改变，第一精细延迟部分的延迟可以不同于第二精细延迟部分的延迟而不同。 不同地调整第一和第二精细延迟部分的延迟导致位于第一模拟延迟部分之后的第一边缘检测器和位于第二模拟延迟部分之后的第二边缘检测器之间的脉冲边缘同步。
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82.发明授权Distributing multiplexing logic to remove multiplexor latency on the output path for variable clock cycle, delayed signals 有权分配多路复用逻辑，以消除可变时钟周期，延迟信号的输出路径上的多路复用器延迟公开(公告)号：US08994424B2
公开(公告)日：2015-03-31
申请号：US13797252
申请日：2013-03-12
发明人： Huu N. Dinh , Robert S. Horton , Bill N. On
CPC分类号： H03K5/159 , H03K3/037 , H03K19/1737 , H03K2005/00104 , H03K2005/00241
摘要： A logic unit is configured with least one multiplexor distributed along a delay path of a logic unit, wherein each at least one multiplexor is configured to receive two inputs and output one of the two inputs, wherein each at least one multiplexor is configured to select one of the two inputs to control a particular programmable number of clock cycles of delay added to a signal from 1 to N clock cycles. The logic unit is configured with at least two latches distributed along the delay path of the logic unit, wherein each at least one latch is configured to add a clock cycle of delay, wherein a terminating latch from among the at least two latches is configured to output the signal delayed by the particular programmable number of clock cycles.
摘要翻译： 逻辑单元配置有沿着逻辑单元的延迟路径分布的至少一个多路复用器，其中每个至少一个复用器被配置为接收两个输入并输出两个输入中的一个，其中每个至少一个多路复用器被配置为选择一个 的两个输入来控制特定的可编程数量的延迟的时钟周期，这些时钟周期被添加到从1到N个时钟周期的信号。 逻辑单元配置有沿着逻辑单元的延迟路径分布的至少两个锁存器，其中每个至少一个锁存器被配置为增加延迟的时钟周期，其中来自所述至少两个锁存器的终止锁存器被配置为 输出延迟特定可编程时钟周期数的信号。
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公开(公告)号：US20140218093A1
公开(公告)日：2014-08-07
申请号：US14200677
申请日：2014-03-07
发明人： Jason T. SU , Winston Lee
CPC分类号： G06F17/5045 , G06F17/5031 , G06F2217/84 , H03K5/159 , H03K2005/00013
摘要： Aspects of the disclosure provide a circuit, such as an integrated circuit. The circuit includes a first circuit and a second circuit. The second circuit includes a delay circuit configured to cause the second circuit to have substantially matched delay characteristics of the first circuit in response to at least one parameter change of manufacturing, environmental and operational parameters, such as process variation, temperature variation, and supply voltage variation.
摘要翻译： 本公开的方面提供了诸如集成电路的电路。 电路包括第一电路和第二电路。 第二电路包括延迟电路，其被配置为响应于制造，环境和操作参数（例如过程变化，温度变化和电源电压）的至少一个参数变化，使得第二电路具有基本匹配的第一电路的延迟特性 变异。
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公开(公告)号：US08742815B2
公开(公告)日：2014-06-03
申请号：US13527908
申请日：2012-06-20
申请人： Sameer Wadhwa , Marzio Pedrali-Noy
发明人： Sameer Wadhwa , Marzio Pedrali-Noy
IPC分类号： H03H11/26
CPC分类号： H03K5/159 , H03K3/356104 , H03K5/133
摘要： Temperature-independent delay elements and oscillators are disclosed. In one design, an apparatus includes at least one delay element, a bias circuit, and a current source. The delay element(s) receive a charging current from the current source and provide a delay that is dependent on the charging current. Each delay element may be a current-starved delay element. The delay element(s) may be coupled in series to implement a delay line or in a loop to implement an oscillator. The bias circuit controls generation of the charging current based on a function of at least one parameter (e.g., a switching threshold voltage) of the at least one delay element in order to reduce variations in delay with temperature. The current source provides the charging current for the delay element(s) and is controlled by the bias circuit.
摘要翻译： 公开了与温度无关的延迟元件和振荡器。 在一种设计中，装置包括至少一个延迟元件，偏置电路和电流源。 延迟元件从电流源接收充电电流并提供取决于充电电流的延迟。 每个延迟元件可以是当前饥饿的延迟元件。 延迟元件可以串联耦合以实现延迟线或在环路中实现振荡器。 偏置电路基于至少一个延迟元件的至少一个参数（例如，开关阈值电压）的功能来控制充电电流的产生，以便减少随温度延迟的变化。 电流源为延迟元件提供充电电流，并由偏置电路控制。
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85.发明申请SEMICONDUCTOR DEVICE USING MULTI-PHASE CLOCK SIGNAL AND INFORMATION PROCESSING SYSTEM INCLUDING THE SAME 有权使用多相时钟信号的半导体器件和包括其的信息处理系统公开(公告)号：US20140132317A1
公开(公告)日：2014-05-15
申请号：US14158253
申请日：2014-01-17
CPC分类号： H03L7/00 , H03K5/133 , H03K5/159 , H03K2005/00032 , H03K2005/00052 , H03L7/0816
摘要： Disclosed herein is a device that includes a delay line that includes n delay circuits cascade-connected and delays an input clock signal by k cycles, and a routing circuit that generates multi-phase clock signals having different phases based on at least a part of n output clock signals output from the n delay circuits, respectively. The n and the k are both integers more than 1 and a greatest common divisor thereof is 1.
摘要翻译： 本文公开了一种包括延迟线的装置，其包括级联的n个延迟电路和将输入时钟信号延迟k个周期的延迟线，以及基于n的至少一部分生成具有不同相位的多相时钟信号的路由电路 输出从n个延迟电路输出的时钟信号。 n和k都是大于1的整数，最大公约数为1。
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86.发明授权Semiconductor device using multi-phase clock signal and information processing system including the same 有权半导体器件采用多相时钟信号和信息处理系统，包括相同的公开(公告)号：US08643413B2
公开(公告)日：2014-02-04
申请号：US13598289
申请日：2012-08-29
IPC分类号： H03L7/00
CPC分类号： H03L7/00 , H03K5/133 , H03K5/159 , H03K2005/00032 , H03K2005/00052 , H03L7/0816
摘要： Disclosed herein is a device that includes a delay line that includes n delay circuits cascade-connected and delays an input clock signal by k cycles, and a routing circuit that generates multi-phase clock signals having different phases based on at least a part of n output clock signals output from the n delay circuits, respectively. The n and the k are both integers more than 1 and a greatest common divisor thereof is 1.
摘要翻译： 本文公开了一种包括延迟线的装置，其包括级联的n个延迟电路和将输入时钟信号延迟k个周期的延迟线，以及基于n的至少一部分生成具有不同相位的多相时钟信号的路由电路 输出从n个延迟电路输出的时钟信号。 n和k都是大于1的整数，最大公约数为1。
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公开(公告)号：US20130038368A1
公开(公告)日：2013-02-14
申请号：US13658581
申请日：2012-10-23
申请人： SK hynix Inc.
发明人： Yong-Hoon KIM , Hyun-Woo LEE
IPC分类号： H03H11/26
摘要： A semiconductor device including a common delay circuit configured to delay an input signal in response to a delay control code to output a first delayed input signal and a second delayed input signal; a first delay circuit configured to delay the first delayed input signal in response to the delay control code and to output a first output signal; and a second delay circuit configured to delay the second delayed input signal in response to the delay control code and to output a second output signal.
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公开(公告)号：US08278988B2
公开(公告)日：2012-10-02
申请号：US12997104
申请日：2008-06-27
申请人： Martin Mienkina , Pavel Grasblum
发明人： Martin Mienkina , Pavel Grasblum
IPC分类号： H03H11/26
摘要： A semiconductor device comprising timer logic for generating a first modulated waveform signal, and delay logic, operably coupled to the timer logic and arranged to provide a first delay in a rising edge of the first modulated waveform signal generated by the timer logic; and provide a second delay in a falling edge of the first modulated waveform generated by the timer logic. The first delay and second delay of the first modulated waveform forms a second, refined modulated waveform signal that comprises a higher frequency resolution than a frequency resolution of the first modulated waveform signal.
摘要翻译： 一种半导体器件，包括用于产生第一调制波形信号的定时器逻辑和延迟逻辑，其可操作地耦合到定时器逻辑并被布置成在定时器逻辑产生的第一调制波形信号的上升沿提供第一延迟; 并且在由定时器逻辑产生的第一调制波形的下降沿提供第二延迟。 第一调制波形的第一延迟和第二延迟形成第二精细调制波形信号，其包括比第一调制波形信号的频率分辨率更高的频率分辨率。
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公开(公告)号：US20110266888A1
公开(公告)日：2011-11-03
申请号：US13180764
申请日：2011-07-12
申请人： Simon Y. London
发明人： Simon Y. London
CPC分类号： H04L25/0278 , H03K3/53 , H03K5/065 , H03K5/159 , H04B1/7174
摘要： A bipolar pulse generator includes two, two-conductor transmission lines coupled together with a load positioned between the two transmission lines. Each conductor of a transmission line we define as a segment. Two segments of one transmission line are charged and switchably coupled to two segments of the other transmission line to produce a bipolar pulse on the matched load. This bipolar pulse generator may be implemented in a flat or a folded design. The generator may include two transmission line structures coupled together with a load positioned between each transmission line structures. The first transmission line structure may include a stepped transmission line and an embedded transmission line segment. A switch may be coupled between the embedded transmission line segment and another segment of the transmission line structure. During operation, the first transmission line structure may be charged to a potential with the switch in the open position and, when the switch is closed, the charge on the first transmission line structure together with the second transmission line structure generates a bipolar pulse on the matched load.
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90.发明授权公开(公告)号：US07701192B2
公开(公告)日：2010-04-20
申请号：US11893776
申请日：2007-08-17
申请人： Steve McCoy , John David Hamre
发明人： Steve McCoy , John David Hamre
IPC分类号： G01R31/00
CPC分类号： G01R31/31937 , G01R31/3016 , G01R31/31708 , H03K5/159
摘要： A method of preparing a signal for measurement includes receiving the signal and selecting a first edge and a second edge within the signal. The method also includes delivering the first edge to a time interval measurement system after expiration of a first delay period and delivering the second edge to a time interval measurement system after expiration of a second delay period.
摘要翻译： 准备用于测量的信号的方法包括接收信号并选择信号内的第一边缘和第二边缘。 该方法还包括在第一延迟周期期满之后将第一边缘递送到时间间隔测量系统，并且在第二延迟周期期满之后将第二边缘递送到时间间隔测量系统。
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