公开(公告)号：US20130038368A1

公开(公告)日：2013-02-14

申请号：US13658581

申请日：2012-10-23

申请人： SK hynix Inc.

发明人： Yong-Hoon KIM ,  Hyun-Woo LEE

IPC分类号： H03H11/26

CPC分类号： H03K5/159 ,  H03K5/15

摘要： A semiconductor device including a common delay circuit configured to delay an input signal in response to a delay control code to output a first delayed input signal and a second delayed input signal; a first delay circuit configured to delay the first delayed input signal in response to the delay control code and to output a first output signal; and a second delay circuit configured to delay the second delayed input signal in response to the delay control code and to output a second output signal.

公开(公告)号：US20150188529A1

公开(公告)日：2015-07-02

申请号：US14643762

申请日：2015-03-10

申请人： SK hynix Inc.

发明人： Yong-Hoon KIM ,  Hyun-Woo LEE

IPC分类号： H03K5/159 ,  H03K5/15

CPC分类号： H03K5/159 ,  H03K5/15

摘要： A semiconductor device including a common delay circuit configured to delay an input signal in response to a delay control code to output a first delayed input signal and a second delayed input signal; a first delay circuit configured to delay the first delayed input signal in response to the delay control code and to output a first output signal; and a second delay circuit configured to delay the second delayed input signal in response to the delay control code and to output a second output signal.

摘要翻译： 一种半导体器件，包括公共延迟电路，配置为响应于延迟控制代码来延迟输入信号以输出第一延迟输入信号和第二延迟输入信号; 第一延迟电路，被配置为响应于所述延迟控制码延迟所述第一延迟输入信号并输出​​第一输出信号; 以及第二延迟电路，被配置为响应于延迟控制代码来延迟第二延迟输入信号并输出​​第二输出信号。

公开(公告)号：US20130120042A1

公开(公告)日：2013-05-16

申请号：US13725065

申请日：2012-12-21

申请人： SK hynix Inc.

发明人： Yong-Hoon KIM ,  Hyun-Woo LEE

IPC分类号： H03L7/08

CPC分类号： H03L7/08 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0812

摘要： A delay locked loop includes a closed loop circuit configured to generate preliminary delay information, a control unit configured to update the preliminary delay information into delay information in response to a control signal, and a first delay unit configured to delay an input clock signal by a first delay value determined by the delay information and generate an output clock signal.

摘要翻译： 延迟锁定环包括被配置为产生初步延迟信息的闭环电路，被配置为响应于控制信号将初步延迟信息更新为延迟信息的控制单元和被配置为将输入时钟信号延迟一个 由延迟信息确定的第一延迟值，并产生输出时钟信号。