公开(公告)号：US20230409202A1

公开(公告)日：2023-12-21

申请号：US18176364

申请日：2023-02-28

申请人： Kioxia Corporation

发明人： Goichi OOTOMO

IPC分类号： G06F3/06

CPC分类号： G06F3/0613 ,  G06F3/0659 ,  G06F3/0679

摘要： A semiconductor storage device includes a plurality of semiconductor memory chips and a bridge chip. The bridge chip includes a first interface connectable to an external memory controller that is external to the semiconductor storage device, a plurality of second interfaces connected to the semiconductor memory chips, and a controller. The controller is configured to, upon receiving, by the first interface, a first command sequence that includes a data transfer command to perform data transfer with one of the semiconductor chips and size information indicating a size of data to be transferred, start an operation to perform the data transfer, and end the operation, upon an amount of data that has been received by the first interface during the data transfer reaching the size indicated by the size information.

公开(公告)号：US20230400997A1

公开(公告)日：2023-12-14

申请号：US18455633

申请日：2023-08-25

申请人： Winbond Electronics Corp.

发明人： Wu-Chuan Cheng ,  Chien-Ti Hou

IPC分类号： G06F3/06 ,  G06F13/16

CPC分类号： G06F3/064 ,  G06F13/1668 ,  G06F3/0671 ,  G06F3/0613

摘要： A memory apparatus embedded with a computing function and an operation method thereof are provided. The memory apparatus includes a memory array, a plurality of data flow controllers, a plurality of computation circuits, a data bus, and a control logic circuit. The memory array includes a plurality of block groups having a plurality of memory blocks. Each of the data flow controllers selects a transmission path of data of each memory block according to a corresponding one of the data flow control signals. In a computation mode, the computation circuit computes first data from the corresponding memory block. In a normal mode, second data is transmitted between the data bus and the corresponding memory block. The data flow controller transmits the first data from the corresponding memory block to the computation circuit according to the data flow control signal provided by the control logic circuit to compute the first data.

公开(公告)号：US11842053B2

公开(公告)日：2023-12-12

申请号：US18084323

申请日：2022-12-19

申请人： Pure Storage, Inc.

发明人： Ronald Karr

IPC分类号： G06F12/00 ,  G06F3/06

CPC分类号： G06F3/0619 ,  G06F3/061 ,  G06F3/064 ,  G06F3/0608 ,  G06F3/0613 ,  G06F3/0655 ,  G06F3/0659 ,  G06F3/0683 ,  G06F3/0688

摘要： A list of a available zones across respective SSD storage portions of a plurality of zoned storage devices of a storage system is maintained. Data is received from multiple sources, wherein the data is associated with processing a dataset, the dataset including multiple volumes and associated metadata. Shards of the data are determined such that each shard is capable of being written in parallel with the remaining shards. The shards are mapped to a subset of the available zones, respectively. The shards are written to the subset of the available zones in parallel.

公开(公告)号：US20230394082A1

公开(公告)日：2023-12-07

申请号：US17833126

申请日：2022-06-06

申请人： Google LLC

发明人： Weiwei Jiang ,  Srinivas Vaduvatha ,  Prashant R. Chandra ,  Jiazhen Zheng ,  Hugh McEvoy Walsh ,  Weihuang Wang ,  Abhishek Agarwal

IPC分类号： G06F3/06 ,  G06F16/901

CPC分类号： G06F3/0659 ,  G06F16/9014 ,  G06F16/9017 ,  G06F3/0613 ,  G06F3/0673

摘要： A hash table system, including a plurality of hash tables, associated with respective hash functions, for storing key-value pairs; an overflow memory for storing key-value pairs moved from the hash tables due to collision; and an arbiter for arbitrating among commands including update commands, match commands, and rehash commands, wherein for each system clock cycle, the arbiter selects as a selected command one of an update command, a match command, or a rehash command, and wherein the hash table system completes execution of each selected command within a bounded number of system clock cycles.

公开(公告)号：US20230376249A1

公开(公告)日：2023-11-23

申请号：US18340810

申请日：2023-06-23

申请人： Rambus Inc.

发明人： Frederick A. Ware ,  Craig E. Hampel ,  Wayne S. Richardson ,  Chad A. Bellows ,  Lawrence Lai

IPC分类号： G06F3/06 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4097 ,  G11C8/06

CPC分类号： G06F3/0659 ,  G11C7/1006 ,  G11C7/1042 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4097 ,  G11C8/06 ,  G06F3/0613 ,  G06F3/0673

摘要： A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval.

公开(公告)号：US20230376247A1

公开(公告)日：2023-11-23

申请号：US18048696

申请日：2022-10-21

申请人： Samsung Electronics Co., Ltd.

发明人： Kwangjin Lee ,  Kirock Kwon ,  Younsoo Cheon

IPC分类号： G06F3/06

CPC分类号： G06F3/0659 ,  G06F3/0656 ,  G06F3/0613 ,  G06F3/0683

摘要： A host system includes a volatile memory device configured to store first temporary data, an embedded storage device configured to store second temporary data, and a host device configured to determine whether to transmit new temporary data to the nonvolatile memory device for storage therein as the first temporary data or to the embedded storage device for storage therein as the second temporary data in response to a detection signal of an event associated with the new temporary data. The embedded storage device may include at least one nonvolatile memory device having a buffer area, in which the second temporary data is stored, and a user area, and a controller configured to control the at least one nonvolatile memory device such that the second temporary data in the buffer area is copied to the user area in response to a flush request of the host device.

公开(公告)号：US20230376207A1

公开(公告)日：2023-11-23

申请号：US18048081

申请日：2022-10-20

申请人： SK hynix Inc.

发明人： Sung Lae OH

IPC分类号： G06F3/06

CPC分类号： G06F3/0613 ,  G06F3/064 ,  G06F3/0679

摘要： A memory device includes a first wafer including a first memory block and a second memory block; and a second wafer arranged in a vertical direction with respect to the first wafer, including a third memory block with a stack number of word lines and a number of strings, each respectively larger than a stack number of word lines and a number of strings of the first memory block and each respectively larger than a stack number of word lines and a number of strings of the second memory block, and sharing, by the third memory block, a plurality of word line drivers with the first memory block and the second memory block.

公开(公告)号：US11822826B2

公开(公告)日：2023-11-21

申请号：US16796196

申请日：2020-02-20

申请人： Raytheon Company

发明人： Russell E. Dube

IPC分类号： G06F3/06 ,  G01S13/02 ,  G06F1/20 ,  G06F13/42 ,  H04L12/06 ,  H04L49/356

CPC分类号： G06F3/067 ,  G01S13/02 ,  G06F1/20 ,  G06F3/0613 ,  G06F3/0646 ,  G06F3/0688 ,  G06F13/4282 ,  H04L12/06 ,  H04L49/358 ,  G06F2200/201 ,  G06F2213/0026

摘要： A storage system for sensor data includes a plurality of storage modules coupled together via a network fabric, each storage module including a plurality of form factor non-volatile memory (NVMe) storage units. The system also includes an integrated processor coupled to the network fabric and storage modules. The integrated processor is configured for control functions and data processing. The integrated processor configuration includes instructions such that the plurality of storage devices receive data via a data centric publish subscribe (DCPS) notification followed by a remote direct memory access (RDMA) transfer.

公开(公告)号：US11816340B2

公开(公告)日：2023-11-14

申请号：US17681999

申请日：2022-02-28

申请人： Dell Products L.P.

发明人： Tal Abir ,  Oshri Adler

IPC分类号： G06F12/00 ,  G06F3/06

CPC分类号： G06F3/0619 ,  G06F3/067 ,  G06F3/0613 ,  G06F3/0659

摘要： Techniques are provided for increasing resiliency of IO operations to network interruptions. One method comprises, in response to a failure of a given IO operation on a first path between at least one initiator of a host device and at least one storage target of a storage volume of a distributed storage system, resending the given IO operation on a second path between the at least one initiator and the at least one storage target; and, in response to a completion of the given IO operation on a given one of the first path and the second path, initiating a remapping of the storage volume. The remapping of the storage volume may comprise unmapping the storage volume and mapping the storage volume. One or more IO operations having an older generation number than the generation number of the storage volume may be discarded.

公开(公告)号：US11809715B2

公开(公告)日：2023-11-07

申请号：US17239460

申请日：2021-04-23

申请人： MICRON TECHNOLOGY, INC.

发明人： Timothy Hollis ,  Roy E. Greeff

IPC分类号： G06F3/06 ,  H04L25/49 ,  G06F13/42 ,  G06F13/40 ,  G11C7/10

CPC分类号： G06F3/0613 ,  G06F3/0607 ,  G06F3/0635 ,  G06F13/4022 ,  G06F13/4072 ,  G06F13/4234 ,  G06F13/4282 ,  G11C7/1072 ,  H04L25/4923

摘要： Apparatuses and methods for multi-level communication architectures are disclosed herein. An example apparatus may include a driver circuit configured to convert a plurality of bitstreams into a plurality of multilevel signals. A count of the plurality of bitstreams is greater than count of the plurality of multilevel signals. The driver circuit further configured to drive the plurality of multilevel signals onto a plurality of signal lines using individual drivers. A driver of the individual drivers is configured to drive more than two voltages.