公开(公告)号：US11960811B2

公开(公告)日：2024-04-16

申请号：US17721982

申请日：2022-04-15

Applicant: Synopsys, Inc.

Inventor： Ningjia Zhu

IPC: G06F30/392 ,  G06F30/327 ,  G06F111/04 ,  G06F111/20 ,  G06F119/06

CPC classification number: G06F30/392 ,  G06F30/327 ,  G06F2111/04 ,  G06F2111/20 ,  G06F2119/06

Abstract: New techniques for the partitioning of big element blocks in a circuit are disclosed. The techniques partition both pre-layout and post-layout circuits. If a post-layout circuit has different simulation results from a pre-layout circuit, the techniques determine where and how “cross-talk” of the RC networks due to RC extraction is changing the circuit physics behavior from the original design of the circuit. A flow of the local circuit simulation of the pre-layout netlist and the post-layout netlist of the same design is presented. A flow of reference or relative or differential circuit simulation of a known design and a new design of the same kind is described. This Abstract is not intended to limit the scope of the claims.

公开(公告)号：US11960794B2

公开(公告)日：2024-04-16

申请号：US18058121

申请日：2022-11-22

Applicant: Autodesk, Inc.

Inventor： Shatakirti Reddy ,  Nirupam Nirupam ,  Pradeep Kumar ,  Sandip Mansukhlal Chauhan

IPC: G06F30/00 ,  G06F40/205 ,  G06F40/284 ,  G06F40/30 ,  G06F111/02 ,  G06F111/20

CPC classification number: G06F30/00 ,  G06F40/30 ,  G06F40/205 ,  G06F40/284 ,  G06F2111/02 ,  G06F2111/20

Abstract: A method, system, and article of manufacture provide for multi-user collaboration on a three-dimensional (3D) design. The 3D design is acquired in a computer-aided design (CAD) application. A commenting process for a comment to be associated with a selected part of the 3D design is activated. Textual user input for the comment is dynamically processed as the comment is received. The processing recognizes that the text relates to creating or modifying the selected part, retrieves a list of alternative parts (based on similarities between the alternative parts and the selected part), and displays a graphic representation of an alternative part. An alternative part is selected and inserted in the comment as a proposed replacement part. The comment including the proposed replacement part is provided to another user.

公开(公告)号：US11907625B2

公开(公告)日：2024-02-20

申请号：US17136259

申请日：2020-12-29

Applicant: Dassault Systemes Simulia Corp.

Inventor： Hiroshi Otomo ,  Rafael Salazar Tio ,  Hudong Chen ,  Raoyang Zhang ,  Andrew Fager ,  Ganapathi Raman Balasubramanian ,  Bernd Crouse ,  Hongli Fan ,  Jingjing Yang

IPC: G06F30/28 ,  G06T7/10 ,  G06F113/08 ,  G06F111/20

CPC classification number: G06F30/28 ,  G06T7/10 ,  G06F2111/20 ,  G06F2113/08

Abstract: Disclosed are computer implemented techniques for conducting a fluid simulation of a porous medium. These techniques involve retrieving a representation of a three dimensional porous medium, the representation including pore space corresponding to the porous medium, with the representation including at least one portion of under-resolved pore structure in the porous medium, defining a representative flow model that includes the under-resolved pore structure in the representation, and constructing by the computer system fluid force curves that correspond to fluid forces in the under-resolved pore structure in the representation.

公开(公告)号：US20240037305A1

公开(公告)日：2024-02-01

申请号：US18481935

申请日：2023-10-05

Applicant: Intel Corporation

Inventor： Kalen Brunham ,  Jakob Engblom

IPC: G06F30/3308 ,  G06F30/327

CPC classification number: G06F30/3308 ,  G06F30/327 ,  G06F2111/20

Abstract: Systems or methods of the present disclosure may provide receiving configuration data corresponding to a circuit design for programmable logic circuitry. A first intellectual property (IP) block is configured using parameterization data of the configuration data. A stub model is generated for a second IP block using interconnect and register data of the configuration data. A chip-level model is generated that represents the circuit design based on the first IP block, the stub model, and memory map data of the configuration data. The chip-level model is consumable by a virtual platform simulator.

公开(公告)号：US11886789B1

公开(公告)日：2024-01-30

申请号：US17369192

申请日：2021-07-07

Applicant: Xilinx, Inc.

Inventor： Ayush Khemka ,  Srinivas Beeravolu ,  Kalyani Tummala ,  Jaipal Reddy Nareddy ,  Adithya Balaji Boda ,  Suman Kumar Timmireddy

IPC: G06F30/392 ,  G06F30/398 ,  G06F111/20

CPC classification number: G06F30/392 ,  G06F30/398 ,  G06F2111/20

Abstract: Circuit design development using block design containers can include opening, within a development environment generated by an Electronic Design Automation (EDA) system, a top-level block design specifying a circuit design and inserting, within the top-level block design using the EDA system, a block design container. The block design container specifies a source block design used as a sub-design within the top-level block design.

公开(公告)号：US20240005080A1

公开(公告)日：2024-01-04

申请号：US17809600

申请日：2022-06-29

Applicant: International Business Machines Corporation

Inventor： LOUIS ZUOGUANG LIU ,  Nianzheng Cao ,  Sae Kyu Lee ,  Zhibin Ren

IPC: G06F30/398 ,  G06F30/392

CPC classification number: G06F30/398 ,  G06F30/392 ,  G06F2111/20

Abstract: Aspects of the invention include systems and methods configured to provide parasitic capacitance-aware dummy metal fill methodologies. A non-limiting example computer-implemented method includes selecting one or more layers in a circuit design layout for interlayer parasitic capacitance reduction. One or more dummy metal shapes in each of the one or more layers selected for interlayer parasitic capacitance reduction is adjusted (e.g., trimmed, moved, and/or reshaped). One or more adjusted dummy metal shapes are modified until the circuit design layout satisfies design rule checking (DRC) analysis and timing is closed.

公开(公告)号：US20230409792A1

公开(公告)日：2023-12-21

申请号：US18079706

申请日：2022-12-12

Applicant: TSINGHUA UNIVERSITY ,  BEIJING SEETRUM TECHNOLOGY CO., LTD.

Inventor： Kaiyu CUI ,  Hongbo ZHU ,  Yidong HUANG ,  Wei ZHANG ,  Xue FENG ,  Fang LIU

IPC: G06F30/337

CPC classification number: G06F30/337 ,  G06F2111/20

Abstract: A spectral chip structure design method includes: obtaining an application-specific spectral library, and determining a spectral principal component based on the application-specific spectral library; performing non-negative processing on the spectral principal component to obtain a non-negative spectral principal component; and determining transmission spectra of the spectral chip structure based on the non-negative spectral principal component. By summarizing spectral features of the application-specific spectral library through the spectral principal component, a quantitative evaluation for the spectral library is realized and then by designing the spectral chip structure on this basis, a targeted quantitative design on the application-specific spectral library can be realized and the accuracy of reconstructing spectra by the spectral chip can be improve

公开(公告)号：US11829194B2

公开(公告)日：2023-11-28

申请号：US17095803

申请日：2020-11-12

Applicant: ESKO Software BVBA

Inventor： Lieven Plettinck ,  Richard C. Deroo ,  Rian Goossens

IPC: G06F30/12 ,  G06K19/06 ,  G06F30/17 ,  G06F111/20

CPC classification number: G06F30/12 ,  G06F30/17 ,  G06K19/06037 ,  G06F2111/20

Abstract: A computer-implemented method for creating a computer-aided design (CAD) corresponding to a 2-dimensional rendering of an unfolded blank configured for manipulation into a 3-dimensional shape. The method includes obtaining a first digital, non-CAD design file containing information relating to the unfolded blank geometry but lacking metadata that defines cut or crease lines separately from surrounding content, and deriving, with a computer processor, a digital representation of the unfolded blank geometry based upon the first digital non-CAD design file. The digital representation includes defined data corresponding to a shape having one or more defined cut and/or crease lines. A system for performing the method includes a computer processor and machine-readable media accessible by the computer processor comprising non-transitory, instructions readable by the computer processor for performing the method steps of defining the digital non-CAD design file and deriving the digital representation therefrom.

公开(公告)号：US20230376671A1

公开(公告)日：2023-11-23

申请号：US18315712

申请日：2023-05-11

Applicant: MediaTek Inc.

Inventor： Jen-Wei Lee ,  Yi-Ying Liao ,  Te-Wei Chen ,  Yu-Hsiu Lin ,  Chia-Wei Chen ,  Chun-Ku Ting ,  Sheng-Tai Tseng ,  Ronald Kuo-Hua Ho ,  Hsin-Chuan Kuo ,  Chun-Chieh Wang ,  Ming-Fang Tsai ,  Chun-Chih Yang ,  Tai-Lai Tung ,  Da-Shan Shiu

IPC: G06F30/398 ,  G06F30/392

CPC classification number: G06F30/398 ,  G06F30/392 ,  G06F2111/20

Abstract: A neural network based method places flexible blocks on a chip canvas in an integrated circuit (IC) design. The neural network receives an input describing geometric features of a flexible block to be placed on the chip canvas. The geometric features includes an area size and multiple aspect ratios. The neural network generates a probability distribution over locations on the chip canvas and the aspect ratios of the flexible block. Based on the probability distribution, a location on the chip canvas is selected for placing the flexible block with a chosen aspect ratio.

公开(公告)号：US20230325546A1

公开(公告)日：2023-10-12

申请号：US18210205

申请日：2023-06-15

Applicant: Canva Pty Ltd

Inventor： Mars Buttfield-Addison

IPC: G06F30/12 ,  G06F30/20 ,  G06F18/22 ,  G06F18/2431 ,  G06F18/2413

CPC classification number: G06F30/12 ,  G06F30/20 ,  G06F2111/20 ,  G06F18/2431 ,  G06F18/24137 ,  G06F18/22

Abstract: Described herein is a computer implemented method for automatically grouping design elements on a page. The method comprises generating one or more sets of groups, each set of groups including one or more groups, each group grouping including one or more of the design elements; calculating set cohesion metrics for at least two of the sets of groups, the set cohesion metric calculated for a given set of groups providing a measure of how well the given set of groups has grouped the design elements on the page; determining, based on the cohesion metrics, a final set of groups; and grouping the design elements according to the one or more groups defined by the final set of groups.