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    INTEGRATED CHIP WITH GRAPHENE BASED INTERCONNECT
    82.
    发明申请
    INTEGRATED CHIP WITH GRAPHENE BASED INTERCONNECT 有权

    公开(公告)号：US20220359413A1

    公开(公告)日：2022-11-10

    申请号：US17308361

    申请日：2021-05-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shin-Yi Yang ,  Meng-Pei Lu ,  Chin-Lung Chung ,  Ming-Han Lee ,  Shau-Lin Shue

    IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L21/3105

    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate. A first conductive feature is over the substrate. A second conductive feature is over the substrate and is adjacent to the first conductive feature. The first and second conductive features are separated by a cavity. A dielectric liner extends from the first conductive feature to the second conductive feature along a bottom of the cavity and further extends along opposing sidewalls of the first and second conductive features. A dielectric cap covers and seals the cavity. The dielectric cap has a top surface that is approximately planar with top surfaces of the first and second conductive features. The first conductive feature and the second conductive feature comprise graphene intercalated with one or more metals.

    Protection liner on interconnect wire to enlarge processing window for overlying interconnect via
    84.
    发明授权
    Protection liner on interconnect wire to enlarge processing window for overlying interconnect via 有权

    公开(公告)号：US11309241B2

    公开(公告)日：2022-04-19

    申请号：US16908942

    申请日：2020-06-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shin-Yi Yang ,  Hsin-Yen Huang ,  Ming-Han Lee ,  Shau-Lin Shue ,  Yu-Chen Chan ,  Meng-Pei Lu

    IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a lower dielectric arranged over a substrate. An interconnect wire is arranged over the dielectric layer, and a first interconnect dielectric layer is arranged outer sidewalls of the interconnect wire. A protection liner that includes graphene is arranged directly on the outer sidewalls of the interconnect wire and on a top surface of the interconnect wire. The integrated chip further includes a first etch stop layer arranged directly on upper surfaces of the first interconnect dielectric layer, and a second interconnect dielectric layer arranged over the first interconnect dielectric layer and the interconnect wire. Further, an interconnect via extends through the second interconnect dielectric layer, is arranged directly over the protection liner, and is electrically coupled to the interconnect wire.

    Method with CMP for Metal Ion Prevention
    88.
    发明申请
    Method with CMP for Metal Ion Prevention 有权

    公开(公告)号：US20210265172A1

    公开(公告)日：2021-08-26

    申请号：US16801526

    申请日：2020-02-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shih-Kang Fu ,  Ming-Han Lee ,  Shau-Lin Shue

    IPC: H01L21/321 ,  H01L21/768 ,  H01L21/02 ,  H01L21/3213 ,  C09G1/02 ,  H01L21/67

    Abstract: The present disclosure provides a method for fabricating a semiconductor structure that includes a first dielectric layer over a semiconductor substrate, and a first cap layer over the first dielectric layer. The method includes forming a first metal feature in the first dielectric layer; performing a first CMP process on the first metal feature using a first rotation rate; and performing a second CMP process on the first metal feature using a second rotation rate slower than the first rotation rate. The second CMP process may be time-based. The second CMP process may stop on the first cap layer. After performing the second CMP process, the method includes removing the first cap layer. The first CMP process may have a first polishing rate to the first metal feature. The second CMP process may have a second polishing rate to the first metal feature lower than the first polishing rate.

    Graphene Barrier Layer
    90.
    发明申请
    Graphene Barrier Layer 有权

    公开(公告)号：US20210082829A1

    公开(公告)日：2021-03-18

    申请号：US16571279

    申请日：2019-09-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shin-Yi Yang ,  Ming-Han Lee ,  Shau-Lin Shue

    IPC: H01L23/532 ,  H01L21/324 ,  H01L23/522 ,  H01L21/768

    Abstract: Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a third dielectric layer over the second dielectric layer, a second contact feature extending through the second dielectric layer and the third dielectric layer, and a graphene layer between the second contact feature and the third dielectric layer.

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