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公开(公告)号：US08711607B2
公开(公告)日：2014-04-29
申请号：US13110068
申请日：2011-05-18
IPC分类号： G11C11/00
CPC分类号： G11C11/419 , G11C5/146 , G11C5/147 , G11C11/4125 , G11C11/417 , G11C2207/2227
摘要： A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.
摘要翻译： 系统LSI中的逻辑电路设置有电源开关，以便在待机时切断开关，从而减少漏电流。 同时，系统LSI的SRAM电路控制衬底偏置以减少漏电流。
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82.发明授权Semiconductor memory device that can stably perform writing and reading without increasing current consumption even with a low power supply voltage 有权半导体存储器件即使在低电源电压下也能够稳定地执行写入和读取而不增加电流消耗公开(公告)号：US08630142B2
公开(公告)日：2014-01-14
申请号：US13492530
申请日：2012-06-08
IPC分类号： G11C5/14
CPC分类号： G11C11/419 , G11C5/063 , G11C11/412
摘要： Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.
摘要翻译： 单元电源线被布置用于存储单元列，并且分别根据相应列中的位线的电压电平来调整单元电源线的阻抗或电压电平。 在数据写入操作中，根据所选列的位线电位将单元电源线强制为浮置状态，并且电压电平改变，并且减小所选存储单元的锁存能力以快速写入数据。 即使使用低电源电压，也可以实现能够稳定地执行数据的写入和读取的静态半导体存储器件。
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83.发明授权Semiconductor integrated circuit device including SRAM memory cells having two P-channel MOS transistors and four N-channel MOS transistors and with four wiring layers serving as their gate electrodes 有权半导体集成电路器件包括具有两个P沟道MOS晶体管和四个N沟道MOS晶体管以及四个布线层作为其栅电极的SRAM存储单元公开(公告)号：US08482083B2
公开(公告)日：2013-07-09
申请号：US12821329
申请日：2010-06-23
CPC分类号： H01L27/1104 , G11C11/412 , G11C11/417 , H01L27/11 , H01L29/4916 , H01L29/783 , Y10S257/904
摘要： Prior known static random access memory (SRAM) cells required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supply power to the substrate are formed in parallel to word lines in such a manner that one region is provided per group of thirty two memory cell rows or sixty four cell rows.
摘要翻译： 现有已知的静态随机存取存储器（SRAM）单元需要将扩散层弯曲成键状形状，以便与其中形成有P型阱区的衬底电接触，这将导致不对称性的降低 导致出现微图案化困难的问题。 为了避免这个问题，构成SRAM单元的逆变器的P型阱区被细分成两部分，它们设置在N型阱区NW1的相对侧上，并形成为扩散 形成晶体管的层没有曲率，同时使得布局方向在平行于阱边界线和位线的方向上运行。 在阵列的中间位置处，用于向衬底供电的区域形成为平行于字线，以这样的方式，每组三十二个存储单元行或六十六个单元行提供一个区域。
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公开(公告)号：US20130049131A1
公开(公告)日：2013-02-28
申请号：US13616435
申请日：2012-09-14
IPC分类号： H01L27/092
CPC分类号： H01L27/1104 , G11C11/412 , G11C11/417 , H01L27/11 , H01L29/4916 , H01L29/783 , Y10S257/904
摘要： Prior known static random access memory (SRAM) cells required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supply power to the substrate are formed in parallel to word lines.
摘要翻译： 现有已知的静态随机存取存储器（SRAM）单元需要将扩散层弯曲成键状形状，以便与其中形成有P型阱区域的衬底电接触，这将导致不对称性的降低 导致微图案化困难。 为了避免这个问题，构成SRAM单元的逆变器的P型阱区被细分成两部分，它们设置在N型阱区NW1的相对侧上，并形成为扩散 形成晶体管的层没有曲率，同时使得布局方向在平行于阱边界线和位线的方向上运行。 在阵列的中间位置处，与基板平行地形成用于向基板供电的区域。
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公开(公告)号：US08325553B2
公开(公告)日：2012-12-04
申请号：US13154919
申请日：2011-06-07
申请人： Kiyoo Itoh , Koichiro Ishibashi
发明人： Kiyoo Itoh , Koichiro Ishibashi
IPC分类号： G11C11/419
CPC分类号： H01L27/105 , G11C11/412 , G11C11/413 , G11C11/417 , H01L27/1104 , H01L27/1116 , Y10S257/903
摘要： A static memory cell, composed of cross-coupled MOS transistors having a relatively high threshold voltage, is equipped with MOS transistors for controlling the power supply line voltage of the memory cell. To permit the voltage difference between two data storage nodes in the inactivated memory cell to exceed the voltage difference between the two nodes when write data is applied from a data line pair DL and /DL to the two nodes in the activated memory cell, the power supply line voltage control transistors are turned on to apply a high voltage VCH to the power supply lines after the word line voltage is turned off. The data holding voltage in the memory cell can be activated to a high voltage independent of the data line voltage, and the data holding voltage can be dynamically set so that read and write operations can be performed at high speed with low power consumption.
摘要翻译： 由具有相对高阈值电压的交叉耦合MOS晶体管组成的静态存储单元配备有用于控制存储单元的电源线电压的MOS晶体管。 为了在从数据线对DL和/ DL向激活的存储单元中的两个节点施加写入数据时，允许非激活存储单元中的两个数据存储节点之间的电压差超过两个节点之间的电压差， 电源线电压控制晶体管导通，在字线电压关闭后，向电源线施加高电压VCH。 存储单元中的数据保持电压可以独立于数据线电压而被激活到高电压，并且可以动态地设置数据保持电压，使得能够以低功耗高速执行读和写操作。
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86.发明授权Semiconductor memory device that can stably perform writing and reading without increasing current consumption even with a low power supply voltage 有权半导体存储器件即使在低电源电压下也能够稳定地执行写入和读取而不增加电流消耗公开(公告)号：US08218390B2
公开(公告)日：2012-07-10
申请号：US13186769
申请日：2011-07-20
IPC分类号： G11C5/14
CPC分类号： G11C11/419 , G11C5/063 , G11C11/412
摘要： Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.
摘要翻译： 单元电源线被布置用于存储单元列，并且分别根据相应列中的位线的电压电平来调整单元电源线的阻抗或电压电平。 在数据写入操作中，根据所选列的位线电位将单元电源线强制为浮置状态，并且电压电平改变，并且减小所选存储单元的锁存能力以快速写入数据。 即使使用低电源电压，也可以实现能够稳定地执行数据的写入和读取的静态半导体存储器件。
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公开(公告)号：US20110235439A1
公开(公告)日：2011-09-29
申请号：US13154919
申请日：2011-06-07
申请人： Kiyoo Itoh , Koichiro Ishibashi
发明人： Kiyoo Itoh , Koichiro Ishibashi
CPC分类号： H01L27/105 , G11C11/412 , G11C11/413 , G11C11/417 , H01L27/1104 , H01L27/1116 , Y10S257/903
摘要： A static memory cell, composed of cross-coupled MOS transistors having a relatively high threshold voltage, is equipped with MOS transistors for controlling the power supply line voltage of the memory cell. To permit the voltage difference between two data storage nodes in the inactivated memory cell to exceed the voltage difference between the two nodes when write data is applied from a data line pair DL and /DL to the two nodes in the activated memory cell, the power supply line voltage control transistors are turned on to apply a high voltage VCH to the power supply lines after the word line voltage is turned off. The data holding voltage in the memory cell can be activated to a high voltage independent of the data line voltage, and the data holding voltage can be dynamically set so that read and write operations can be performed at high speed with low power consumption.
摘要翻译： 由具有相对高阈值电压的交叉耦合MOS晶体管组成的静态存储单元配备有用于控制存储单元的电源线电压的MOS晶体管。 为了在从数据线对DL和/ DL向激活的存储单元中的两个节点施加写入数据时，允许非激活存储单元中的两个数据存储节点之间的电压差超过两个节点之间的电压差， 电源线电压控制晶体管导通，在字线电压关闭后，向电源线施加高电压VCH。 存储单元中的数据保持电压可以独立于数据线电压而被激活到高电压，并且可以动态地设置数据保持电压，使得能够以低功耗高速执行读和写操作。
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88.发明授权Semiconductor memory device that can stably perform writing and reading without increasing current consumption even with a low power supply voltage 有权半导体存储器件即使在低电源电压下也能够稳定地执行写入和读取而不增加电流消耗公开(公告)号：US08009500B2
公开(公告)日：2011-08-30
申请号：US12367871
申请日：2009-02-09
IPC分类号： G11C5/14
CPC分类号： G11C11/419 , G11C5/063 , G11C11/412
摘要： Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.
摘要翻译： 单元电源线被布置用于存储单元列，并且分别根据相应列中的位线的电压电平来调整单元电源线的阻抗或电压电平。 在数据写入操作中，根据所选列的位线电位将单元电源线强制为浮置状态，并且电压电平改变，并且减小所选存储单元的锁存能力以快速写入数据。 即使使用低电源电压，也可以实现能够稳定地执行数据的写入和读取的静态半导体存储器件。
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公开(公告)号：US07781846B2
公开(公告)日：2010-08-24
申请号：US12348524
申请日：2009-01-05
CPC分类号： H01L27/1104 , G11C11/412 , G11C11/417 , H01L27/11 , H01L29/4916 , H01L29/783 , Y10S257/904
摘要： Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.
摘要翻译： 现有的已知的静态随机存取存储器（SRAM）单元需要将扩散层弯曲成键状形状，以便与其中形成有P型阱区的衬底进行电接触，这将导致 不对称性导致了微图案化困难的问题的发生。 为了避免这个问题，构成SRAM单元的逆变器的P型阱区被细分成两部分，它们设置在N型阱区NW1的相对侧上，并形成为扩散 形成晶体管的层没有曲率，同时使得布局方向在平行于阱边界线和位线的方向上运行。 在阵列的中间位置处，以与字线平行的方式形成用于向基板供电的区域，以每组三十二个存储单元行或六十四个单元行提供一个区域。
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公开(公告)号：US07646662B2
公开(公告)日：2010-01-12
申请号：US12325783
申请日：2008-12-01
IPC分类号： G11C5/14
CPC分类号： G11C11/419 , G11C5/146 , G11C5/147 , G11C11/4125 , G11C11/417 , G11C2207/2227
摘要： A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.
摘要翻译： 系统LSI中的逻辑电路具有电源开关，以便在待机时切断开关，从而减少漏电流。 同时，系统LSI的SRAM电路控制衬底偏置以减少漏电流。
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