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    Multi bit flash memory device and method of programming the same
    81.
    发明申请
    Multi bit flash memory device and method of programming the same 有权
    多位闪存器件及其编程方法相同

    公开(公告)号：US20080137416A1

    公开(公告)日：2008-06-12

    申请号：US12000209

    申请日：2007-12-11

    申请人： Seung-Jae Lee

    发明人： Seung-Jae Lee

    IPC分类号： G11C16/04 ,  G11C16/06

    CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621

    摘要： A method of programming a flash memory device may include dividing a plurality of memory cells into a plurality of groups according to a threshold voltage state, the memory cells configured to store multi bit data. The plurality of memory cells may be programmed with a program data. The memory cells of the divided groups may be respectively selected and programmed by divided group during the programming of the plurality of memory cells.

    摘要翻译： 一种对闪速存储器件进行编程的方法可以包括根据阈值电压状态将多个存储器单元分成多个组，存储器单元被配置为存储多位数据。 多个存储器单元可以用程序数据编程。 在多个存储单元的编程期间，分割组的存储单元可以分别被分组选择和编程。

    Method For Restricting Content Usage In Digital Rights Management
    82.
    发明申请
    Method For Restricting Content Usage In Digital Rights Management 审中-公开
    限制数字权限管理中内容使用的方法

    公开(公告)号：US20080092244A1

    公开(公告)日：2008-04-17

    申请号：US11814776

    申请日：2006-04-06

    申请人： Seung-Jae Lee

    发明人： Seung-Jae Lee

    IPC分类号： H04L9/32

    CPC分类号： H04L63/10 ,  G06F21/10 ,  G06F2221/2111

    摘要： A method for restricting content usage in a digital rights management, in which in order to restrict or grant content usage in a certain geographic location, a geographic usage condition is additionally included in an RO of the content, and a terminal which downloads the RO checks the geographic usage condition to thus restrict or grant the using of the content in the corresponding location or area, wherein the geographic usage condition includes an item for restricting the protected using of the content and/or an item for granting the same, each item including information related to a location or area.

    摘要翻译： 一种用于限制数字版权管理中的内容使用的方法，其中为了限制或授予特定地理位置中的内容使用，地理使用条件另外包括在内容的RO中，并且下载RO检查的终端 地理使用条件，从而限制或批准在相应位置或区域中的内容的使用，其中地理使用条件包括用于限制内容的受保护使用的项目和/或用于授予该内容的项目，每个项目包括 与位置或区域相关的信息。

    Shallow trench isolation structure with converted liner layer
    83.
    发明授权
    Shallow trench isolation structure with converted liner layer 有权
    浅沟槽隔离结构具有转换内衬层

    公开(公告)号：US07163869B2

    公开(公告)日：2007-01-16

    申请号：US10947481

    申请日：2004-09-22

    申请人： Shin-Hye Kim ,  Min Kim ,  Seung-Jae Lee

    发明人： Shin-Hye Kim ,  Min Kim ,  Seung-Jae Lee

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76224

    摘要： A STI (shallow trench isolation) structure is formed with a liner layer that is converted from an initial material to a subsequent material. For example, the liner layer is initially comprised of nitride during wet etch-back of a dielectric fill material comprised of oxide to protect an oxide layer on a semiconductor substrate. Thereafter, an exposed portion of the liner layer is converted into the subsequent material of oxide to protect the dielectric fill material within the STI opening during etching away of masking layers to prevent formation of dents in the STI structure.

    摘要翻译： STI（浅沟槽隔离）结构形成有从初始材料转换成后续材料的衬里层。 例如，在由氧化物构成的介电填充材料的湿法回蚀期间，衬垫层最初由氮化物组成，以保护半导体衬底上的氧化物层。 此后，衬里层的暴露部分被转换成随后的氧化物材料，以在蚀刻掉掩模层期间保护STI开口内的介电填充材料，以防止在STI结构中形成凹痕。

    Flash memory device having single page buffer structure and related programming operations
    84.
    发明申请
    Flash memory device having single page buffer structure and related programming operations 有权
    具有单页缓冲结构和相关编程操作的闪存设备

    公开(公告)号：US20070002615A1

    公开(公告)日：2007-01-04

    申请号：US11347216

    申请日：2006-02-06

    申请人： Seung-Jae Lee ,  Jin-Sung Park

    发明人： Seung-Jae Lee ,  Jin-Sung Park

    IPC分类号： G11C16/04

    CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/24 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2216/14

    摘要： A flash memory device is provided, and the flash memory device comprises memory cells, a sense node connected to a selected bit line, a load circuit connected to the sense node, and first and second sense and register circuits, each connected to the sense node. The first sense and register circuit is configured to store a first data value in accordance with the voltage level of the sense node during an initial read interval of a multi-bit program operation. The load circuit is configured to selectively pre-charge the sense node in accordance with the data value stored in the first sense and register circuit during a verify read interval of the multi-bit program operation. A multi-bit programming method for the flash memory device is also provided.

    摘要翻译： 提供闪速存储器件，并且闪速存储器件包括存储器单元，连接到所选位线的感测节点，连接到感测节点的负载电路以及连接到感测节点的第一和第二感测和寄存器电路 。 第一感测和寄存器电路被配置为在多位程序操作的初始读取间隔期间根据感测节点的电压电平来存储第一数据值。 负载电路被配置为在多位程序操作的验证读取间隔期间根据存储在第一感测和寄存器电路中的数据值选择性地预充电感测节点。 还提供了一种用于闪速存储器件的多位编程方法。

    Method of manufacturing transistor having recessed channel
    85.
    发明授权
    Method of manufacturing transistor having recessed channel 失效
    制造具有凹槽的晶体管的方法

    公开(公告)号：US07125774B2

    公开(公告)日：2006-10-24

    申请号：US10937532

    申请日：2004-09-08

    申请人： Min Kim ,  Ju-Bum Lee ,  Hyeon-Deok Lee ,  Seung-Jae Lee

    发明人： Min Kim ,  Ju-Bum Lee ,  Hyeon-Deok Lee ,  Seung-Jae Lee

    IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L21/3205

    CPC分类号： H01L29/66621 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823487 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7835

    摘要： A method of fabricating a transistor with a recessed channel is provided. The method includes forming trenches for a recessed channel on a semiconductor substrate, depositing an isolation layer on the semiconductor substrate on which the trenches are formed, depositing a gate dielectric layer on the semiconductor substrate so that the gate dielectric layer can be extended to bottoms and sidewalls of the trenches, forming gates to fill the trenches, and forming source and drain regions in the semiconductor substrate adjacent to the gates.

    摘要翻译： 提供一种制造具有凹槽的晶体管的方法。 该方法包括在半导体衬底上形成用于凹陷沟道的沟槽，在其上形成有沟槽的半导体衬底上沉积隔离层，在半导体衬底上沉积栅极电介质层，使得栅极电介质层可以延伸到底部， 沟槽的侧壁，形成用于填充沟槽的栅极，以及在与栅极相邻的半导体衬底中形成源区和漏区。

    Nonvolatile memory device with load-free wired-or structure and an associated driving method
    87.
    发明申请
    Nonvolatile memory device with load-free wired-or structure and an associated driving method 有权
    非易失性存储器件，具有无负载的有线或结构以及相关的驱动方法

    公开(公告)号：US20060152976A1

    公开(公告)日：2006-07-13

    申请号：US11319324

    申请日：2005-12-27

    申请人： Seung-Jae Lee

    发明人： Seung-Jae Lee

    IPC分类号： G11C16/04

    CPC分类号： G11C16/3459 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3454

    摘要： A nonvolatile semiconductor memory device includes an internal output line, and a page buffers. Each page buffer is coupled to at least one bitline, the internal output line, and a data input line physically distinct from the internal output line, and configured to pull the internal output line to an output drive voltage in response to a bitline voltage on one of the bitlines coupled to the page buffer.

    摘要翻译： 非易失性半导体存储器件包括内部输出线和页缓冲器。 每个页缓冲器耦合到至少一个位线，内部输出线和物理上不同于内部输出线的数据输入线，并且被配置为响应于一个位线电压将内部输出线拉到输出驱动电压 的位线耦合到页面缓冲区。

    Gate electrode of a semiconductor device and method of forming the same
    88.
    发明授权
    Gate electrode of a semiconductor device and method of forming the same 失效
    半导体器件的栅电极及其形成方法

    公开(公告)号：US07074671B2

    公开(公告)日：2006-07-11

    申请号：US10626096

    申请日：2003-07-23

    申请人： Seung-Jae Lee ,  Jin-Gi Hong

    发明人： Seung-Jae Lee ,  Jin-Gi Hong

    IPC分类号： H01L21/336

    CPC分类号： H01L29/42324 ,  H01L21/28273

    摘要： Disclosed are an electrode of a semiconductor device and a method of forming the same. A polysilicon layer is formed on a semiconductor substrate. An amorphous silicon capping layer is then formed on the polysilicon layer. A silicide layer is formed on the capping layer. The capping layer prevents chlorine ions from diffusing downward to the polysilicon layer. Accordingly, abnormal growth of the polysilicon layer can be prevented, thus improving the stability of the electrical characteristics of a semiconductor device electrode.

    摘要翻译： 公开了半导体器件的电极及其形成方法。 在半导体基板上形成多晶硅层。 然后在多晶硅层上形成非晶硅覆盖层。 在覆盖层上形成硅化物层。 封盖层防止氯离子向下扩散到多晶硅层。 因此，可以防止多晶硅层的异常生长，从而提高半导体器件电极的电特性的稳定性。

    Shallow trench isolation structure with converted liner layer
    89.
    发明申请
    Shallow trench isolation structure with converted liner layer 有权
    浅沟槽隔离结构具有转换内衬层

    公开(公告)号：US20050167778A1

    公开(公告)日：2005-08-04

    申请号：US10947481

    申请日：2004-09-22

    申请人： Shin-Hye Kim ,  Min Kim ,  Seung-Jae Lee

    发明人： Shin-Hye Kim ,  Min Kim ,  Seung-Jae Lee

    IPC分类号： H01L21/762 ,  H01L21/76 ,  H01L29/00

    CPC分类号： H01L21/76224

    摘要： A STI (shallow trench isolation) structure is formed with a liner layer that is converted from an initial material to a subsequent material. For example, the liner layer is initially comprised of nitride during wet etch-back of a dielectric fill material comprised of oxide to protect an oxide layer on a semiconductor substrate. Thereafter, an exposed portion of the liner layer is converted into the subsequent material of oxide to protect the dielectric fill material within the STI opening during etching away of masking layers to prevent formation of dents in the STI structure.

    摘要翻译： STI（浅沟槽隔离）结构形成有从初始材料转换成后续材料的衬里层。 例如，在由氧化物构成的介电填充材料的湿法回蚀期间，衬垫层最初由氮化物组成，以保护半导体衬底上的氧化物层。 此后，衬里层的暴露部分被转换成随后的氧化物材料，以在蚀刻掉掩模层期间保护STI开口内的介电填充材料，以防止在STI结构中形成凹痕。

    Method of manufacturing transistor having recessed channel
    90.
    发明申请
    Method of manufacturing transistor having recessed channel 失效
    制造具有凹槽的晶体管的方法

    公开(公告)号：US20050054163A1

    公开(公告)日：2005-03-10

    申请号：US10937532

    申请日：2004-09-08

    申请人： Min Kim ,  Ju-Bum Lee ,  Hyeon-Deok Lee ,  Seung-Jae Lee

    发明人： Min Kim ,  Ju-Bum Lee ,  Hyeon-Deok Lee ,  Seung-Jae Lee

    IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/78

    CPC分类号： H01L29/66621 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823487 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7835

    摘要： A method of fabricating a transistor with a recessed channel is provided. The method includes forming trenches for a recessed channel on a semiconductor substrate, depositing an isolation layer on the semiconductor substrate on which the trenches are formed, depositing a gate dielectric layer on the semiconductor substrate so that the gate dielectric layer can be extended to bottoms and sidewalls of the trenches, forming gates to fill the trenches, and forming source and drain regions in the semiconductor substrate adjacent to the gates.

    摘要翻译： 提供一种制造具有凹槽的晶体管的方法。 该方法包括在半导体衬底上形成用于凹陷沟道的沟槽，在其上形成有沟槽的半导体衬底上沉积隔离层，在半导体衬底上沉积栅极电介质层，使得栅极电介质层可以延伸到底部， 沟槽的侧壁，形成用于填充沟槽的栅极，以及在与栅极相邻的半导体衬底中形成源区和漏区。