公开(公告)号：US20130178053A1

公开(公告)日：2013-07-11

申请号：US13782678

申请日：2013-03-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ying Li ,  Henry K. Utomo

IPC: H01L29/40

CPC classification number: H01L29/401 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76897 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656

Abstract: A dielectric liner is formed on sidewalls of a gate stack and a lower contact-level dielectric material layer is deposited on the dielectric liner and planarized. The dielectric liner is recessed relative to the top surface of the lower contact-level dielectric material layer and the top surface of the gate stack. A dielectric metal oxide layer is deposited and planarized to form a dielectric metal oxide spacer that surrounds an upper portion of the gate stack. The dielectric metal oxide layer has a top surface that is coplanar with a top surface of the planarized lower contact-level dielectric material layer. Optionally, the conductive material in the gate stack may be replaced. After deposition of at least one upper contact-level dielectric material layer, at least one via hole extending to a semiconductor substrate is formed employing the dielectric metal oxide spacer as a self-aligning structure.

Abstract translation: 电介质衬垫形成在栅叠层的侧壁上，下电触头层介质材料层沉积在电介质衬垫上并进行平面化处理。 电介质衬垫相对于下接触电介质材料层的顶表面和栅极堆叠的顶表面凹陷。 介电金属氧化物层被沉积并平坦化以形成围绕栅叠层的上部的电介质金属氧化物间隔物。 电介质金属氧化物层具有与平坦化的下接触电介质材料层的顶表面共面的顶表面。 可选地，可以更换栅叠层中的导电材料。 在沉积至少一个上接触电介质材料层之后，使用介电金属氧化物间隔物作为自对准结构形成延伸到半导体衬底的至少一个通孔。