公开(公告)号：US20140253570A1

公开(公告)日：2014-09-11

申请号：US13788209

申请日：2013-03-07

Applicant: APPLE INC.

Inventor： Brijesh Tripathi ,  Peter F. Holland ,  Timothy J. Millet

IPC: G06T1/60

CPC classification number: G06T1/60 ,  G09G5/006 ,  G09G2340/0442 ,  G09G2340/0492 ,  G09G2360/125 ,  G09G2370/10

Abstract: In an embodiment, a system includes hardware optimized for communication to a network display. The hardware may include a display pipe unit that is configured to composite one or more static images and one or more frames from video sequences to form frames for display by a network display. The display pipe unit may include a writeback unit configured to write the composite frames back to memory, from which the frames can be optionally encoded using video encoder hardware and packetized for transmission over a network to a network display. In an embodiment, the display pipe unit may be configured to issue interrupts to the video encoder during generation of a frame, to overlap encoding and frame generation.

Abstract translation: 在一个实施例中，系统包括针对与网络显示器进行通信而优化的硬件。 硬件可以包括显示管单元，其被配置为将来自视频序列的一个或多个静态图像和一个或多个帧组合以形成用于由网络显示器显示的帧。 显示管单元可以包括写回单元，其被配置为将复合帧写回到存储器，可以使用视频编码器硬件来选择性地对帧进行编码，并将其分组化以便通过网络传输到网络显示器。 在一个实施例中，显示管单元可以被配置为在帧的生成期间向视频编码器发出中断，以重叠编码和帧生成。

公开(公告)号：US08719509B2

公开(公告)日：2014-05-06

申请号：US13755999

申请日：2013-01-31

Applicant: Apple Inc.

Inventor： James Wang ,  Zongjian Chen ,  James B. Keller ,  Timothy J. Millet

IPC: G06F13/00

CPC classification number: G06F12/128 ,  G06F12/0864 ,  G06F12/121 ,  G06F12/123

Abstract: In an embodiment, a cache stores tags for cache blocks stored in the cache. Each tag may include an indication identifying which of two or more replacement policies supported by the cache is in use for the corresponding cache block, and a replacement record indicating the status of the corresponding cache block in the replacement policy. Requests may include a replacement attribute that identifies the desired replacement policy for the cache block accessed by the request. If the request is a miss in the cache, a cache block storage location may be allocated to store the corresponding cache block. The tag associated with the cache block storage location may be updated to include the indication of the desired replacement policy, and the cache may manage the block in accordance with the policy. For example, in an embodiment, the cache may support both an LRR and an LRU policy.

Abstract translation: 在一个实施例中，高速缓存存储存储在高速缓存中的高速缓存块的标签。 每个标签可以包括标识由高速缓存支持的两个或多个替换策略中哪一个正在用于对应的高速缓存块的指示，以及指示替换策略中对应的高速缓存块的状态的替换记录。 请求可以包括标识用于请求访问的高速缓存块的期望替换策略的替换属性。 如果请求是高速缓存中的错过，则可以分配高速缓存块存储位置以存储对应的高速缓存块。 与高速缓存块存储位置相关联的标签可以被更新以包括期望的替换策略的指示，并且高速缓存可以根据策略来管理块。 例如，在一个实施例中，高速缓存可以支持LRR和LRU策略。

公开(公告)号：US20140122908A1

公开(公告)日：2014-05-01

申请号：US14149922

申请日：2014-01-08

Applicant: Apple Inc.

Inventor： Josh P. de Cesare ,  Jung Wook Cho ,  Toshinari Takayanagi ,  Timothy J. Millet

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3237 ,  G06F1/3287 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/17 ,  Y02D10/171 ,  Y02D50/20

Abstract: In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state.

Abstract translation: 在一个实施例中，功率管理单元（PMU）可以自动地（在硬件中）转换系统中的一个或多个性能域的性能状态。 性能域要转换到的目标性能状态可以通过软件在PMU中编程，并且软件可以向PMU发信号通知系统中的处理器进入睡眠状态。 PMU可以控制性能域到目标性能状态的转换，并且可能导致处理器进入睡眠状态。 在一个实施例中，PMU可以是可编程的，当处理器退出睡眠状态时，性能域将转换到第二组目标性能状态。 PMU可以控制性能域到第二目标性能状态的转换，并使处理器退出睡眠状态。

公开(公告)号：US20130151781A1

公开(公告)日：2013-06-13

申请号：US13755999

申请日：2013-01-31

Applicant: Apple Inc.

Inventor： James Wang ,  Zongjian Chen ,  James B. Keller ,  Timothy J. Millet

IPC: G06F12/12 ,  G06F12/08

CPC classification number: G06F12/128 ,  G06F12/0864 ,  G06F12/121 ,  G06F12/123

Abstract: In an embodiment, a cache stores tags for cache blocks stored in the cache. Each tag may include an indication identifying which of two or more replacement policies supported by the cache is in use for the corresponding cache block, and a replacement record indicating the status of the corresponding cache block in the replacement policy. Requests may include a replacement attribute that identifies the desired replacement policy for the cache block accessed by the request. If the request is a miss in the cache, a cache block storage location may be allocated to store the corresponding cache block. The tag associated with the cache block storage location may be updated to include the indication of the desired replacement policy, and the cache may manage the block in accordance with the policy. For example, in an embodiment, the cache may support both an LRR and an LRU policy.

Abstract translation: 在一个实施例中，高速缓存存储存储在高速缓存中的高速缓存块的标签。 每个标签可以包括标识由高速缓存支持的两个或多个替换策略中哪一个正在用于对应的高速缓存块的指示，以及指示替换策略中对应的高速缓存块的状态的替换记录。 请求可以包括标识用于请求访问的高速缓存块的期望替换策略的替换属性。 如果请求是高速缓存中的错过，则可以分配高速缓存块存储位置以存储对应的高速缓存块。 与高速缓存块存储位置相关联的标签可以被更新以包括期望的替换策略的指示，并且高速缓存可以根据策略来管理块。 例如，在一个实施例中，高速缓存可以支持LRR和LRU策略。

公开(公告)号：US20130039432A1

公开(公告)日：2013-02-14

申请号：US13651181

申请日：2012-10-12

Applicant: Apple Inc.

Inventor： Haitao Guo ,  Sally Fung ,  Timothy J. Millet

IPC: H04N7/26

CPC classification number: H04N19/86

Abstract: A technique is provided for processing decoded video data to mask visual compression artifacts resulting from video compression. In accordance with this technique, a hardware block is provided for generating and adding random noise to the decoded video stream. In one embodiment, a random number is generated for each pixel of the decoded video data and compared against one or more threshold values to determine a threshold range. In such an embodiment, a noise addend value is selected based upon the threshold comparison and summed with the current pixel. While the present technique may not eliminate the compression artifacts, the addition of random noise renders the compression artifacts less noticeable to the human eye and, therefore, more aesthetically pleasing to a viewer.