公开(公告)号：US20060160286A1

公开(公告)日：2006-07-20

申请号：US11385217

申请日：2006-03-20

Applicant: Eung-Rim Hwang ,  Se-Aug Jang ,  Tae-Woo Jung ,  Seo-Min Kim ,  Woo-Jin Kim ,  Hyung-Soon Park ,  Young-Bog Kim ,  Hong-Seon Yang ,  Hyun-Chul Sohn

Inventor： Eung-Rim Hwang ,  Se-Aug Jang ,  Tae-Woo Jung ,  Seo-Min Kim ,  Woo-Jin Kim ,  Hyung-Soon Park ,  Young-Bog Kim ,  Hong-Seon Yang ,  Hyun-Chul Sohn

IPC: H01L21/338 ,  H01L21/336

CPC classification number: H01L27/11521 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/115 ,  H01L29/7886

Abstract: Disclosed are a memory device and a method for fabricating the same. The memory device includes: a substrate provided with a trench; a bit line contact junction formed beneath the trench; a plurality of storage node contact junctions formed outside the trench; and a plurality of gate structures each being formed on the substrate disposed between the bit line contact junction and one of the storage node contact junctions. Each sidewall of the trench becomes a part of the individual channels and thus, channel lengths of the transistors in the cell region become elongated. Accordingly, the storage node contact junctions have a decreased level of leakage currents, thereby increasing data retention time.

公开(公告)号：US20060022249A1

公开(公告)日：2006-02-02

申请号：US11053704

申请日：2005-02-07

Applicant: Se-Aug Jang ,  Tae-Woo Jung ,  Seo-Min Kim ,  Woo-Jin Kim ,  Hyung-Soon Park ,  Young-Bog Kim ,  Hong-Seon Yang ,  Hyun-Chul Sohn ,  Eung-Rim Hwang

Inventor： Se-Aug Jang ,  Tae-Woo Jung ,  Seo-Min Kim ,  Woo-Jin Kim ,  Hyung-Soon Park ,  Young-Bog Kim ,  Hong-Seon Yang ,  Hyun-Chul Sohn ,  Eung-Rim Hwang

IPC: H01L21/8242 ,  H01L29/94

CPC classification number: H01L27/11521 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/115 ,  H01L29/7886

Abstract: Disclosed are a memory device and a method for fabricating the same. The memory device includes: a substrate provided with a trench; a bit line contact junction formed beneath the trench; a plurality of storage node contact junctions formed outside the trench; and a plurality of gate structures each being formed on the substrate disposed between the bit line contact junction and one of the storage node contact junctions. Each sidewall of the trench becomes a part of the individual channels and thus, channel lengths of the transistors in the cell region become elongated. Accordingly, the storage node contact junctions have a decreased level of leakage currents, thereby increasing data retention time.

公开(公告)号：US06972740B2

公开(公告)日：2005-12-06

申请号：US10425541

申请日：2003-04-28

Applicant: Soo-Jin Lee ,  Woo-Jin Kim ,  Im-Su Choi

Inventor： Soo-Jin Lee ,  Woo-Jin Kim ,  Im-Su Choi

IPC: G09G3/20 ,  G09G3/28

CPC classification number: G09G3/2007 ,  G09G3/296 ,  G09G2320/0257 ,  G09G2320/0626 ,  G09G2360/16

Abstract: An after-image prevention apparatus and method for a plasma display panel having a plurality of address electrodes and a plurality of scan and sustain electrodes arranged in pairs and in a zigzag pattern. An average signal level until the current frame from currently input picture data and an average signal level of each cell until the previous frame as stored in a memory section is calculated. The average signal level is compared with the picture data. An attenuation coefficient is generated corresponding to the difference between the average signal level and the picture data. The picture data is multiplied by the attenuation coefficient to output correction data, thereby preventing an after-image phenomenon on the plasma display panel.

Abstract translation: 一种用于等离子体显示面板的后置图像防止装置和方法，其具有多个地址电极和成对地布置成Z字形图案的多个扫描和维持电极。 计算从当前输入图像数据起的当前帧直到存储在存储器部分中的前一帧之前的每个单元的平均信号电平的平均信号电平。 将平均信号电平与图像数据进行比较。 根据平均信号电平和图像数据之间的差异产生衰减系数。 图像数据乘以衰减系数以输出校正数据，从而防止等离子体显示面板上的后图像现象。

公开(公告)号：US20050140593A1

公开(公告)日：2005-06-30

申请号：US10992210

申请日：2004-11-19

Applicant: Geun-Yeong Chang ,  Woo-Jin Kim

Inventor： Geun-Yeong Chang ,  Woo-Jin Kim

IPC: H04N5/66 ,  G09F9/313 ,  G09G3/20 ,  G09G3/28 ,  G09G3/288 ,  G09G3/291 ,  G09G3/294 ,  G09G3/298 ,  G09G5/02 ,  H01J17/49

CPC classification number: G09G3/288 ,  G09G2320/0626 ,  G09G2330/02 ,  G09G2330/045 ,  G09G2360/16

Abstract: A method and apparatus for driving a plasma display panel that automatically controls power using an average signal level that is compensated based on a difference between power consumption at red (R), green (G), and blue (B) discharge cells. The method includes calculating R, G, and B average signal levels, calculating a compensated average signal level using the R, G, and B average signal levels and R, G, and B weights, and controlling the number of discharges for each frame, which is in inversely proportional to the compensated average signal level. The R, G, and B weights are set at a value that reduces a difference between power consumption at the R, G, and B colored discharge cells when displaying the R, G, and B colors in a case where the R, G, and B average signal levels are equal to each other.

Abstract translation: 一种用于驱动等离子体显示面板的方法和装置，其使用基于红色（R），绿色（G）和蓝色（B）放电单元的功率消耗之间的差异来补偿的平均信号电平来自动控制功率。 该方法包括计算R，G和B平均信号电平，使用R，G和B平均信号电平和R，G和B权重来计算补偿的平均信号电平，并且控制每帧的放电次数， 其与补偿的平均信号电平成反比。 将R，G和B权重设定为在R，G和B着色放电单元上显示R，G和B颜色时的功耗之差减小的值， B平均信号电平相等。

公开(公告)号：US06800907B2

公开(公告)日：2004-10-05

申请号：US10330341

申请日：2002-12-30

Applicant: Jae-Ok Kim ,  Woo-Jin Kim ,  Jong-Hyuk Oh

Inventor： Jae-Ok Kim ,  Woo-Jin Kim ,  Jong-Hyuk Oh

IPC: H01L2362

CPC classification number: H01L29/6659 ,  H01L21/28061 ,  H01L29/4933 ,  H01L29/6656 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a method for fabricating a semiconductor device capable of suppressing stresses concentrated at bottom corners of a gate electrode as simultaneously as preventing an oxidation of a metal included in a gate electrode. The inventive method includes the steps of: forming a gate oxide layer on a substrate; forming a gate electrode including at least one metal layer on the gate oxide layer; forming an oxide layer on the substrate including the gate electrode at a temperature lower than oxidation temperature of the metal layer; and etching selectively the densified oxide layer so as to form an oxide spacer on the lateral sides of the gate electrode.

Abstract translation: 本发明提供一种制造半导体器件的方法，该半导体器件能够同时抑制栅电极中包含的金属的氧化同时抑制集中在栅电极的底角的应力。 本发明的方法包括以下步骤：在衬底上形成栅氧化层; 在所述栅极氧化物层上形成包括至少一个金属层的栅电极; 在比所述金属层的氧化温度低的温度下在包括所述栅电极的所述基板上形成氧化物层; 并选择性地蚀刻致密的氧化物层，以在栅电极的侧面上形成氧化物间隔物。

公开(公告)号：US06581651B2

公开(公告)日：2003-06-24

申请号：US10033834

申请日：2001-12-26

Applicant: Woo Jin Kim ,  Yei Seak Park ,  Byung Kuk Kang

Inventor： Woo Jin Kim ,  Yei Seak Park ,  Byung Kuk Kang

IPC: B65B104

CPC classification number: F16F9/43

Abstract: A gas filling apparatus for gas shock absorber comprises the assembly location correction unit, a gas filling unit, wherein the gas filling unit includes a rod chucking unit, a calking jig, an oil seal pushing unit, and a jig housing. A gas filling method for gas shock absorber comprises the steps of correcting the assembly location of the tube assembly and the rod guide, clamping the base shell assembly; lowering the gas filling unit primarily, lowering the rod chucking unit, lowering the collet housing device; letting the oil seal break away, filling the gas, lowering the gas filling unit secondarily and simultaneously calking primarily, and calking secondarily the base shell assembly. The apparatus and the method need not punch a hole for filling the gas at a circumference of the base shell assembly when filling the gas into a base shell assembly of the gas shock absorber.

Abstract translation: 一种用于气体减震器的气体填充装置包括组装位置校正单元，气体填充单元，其中气体填充单元包括杆夹持单元，压盖夹具，油封推动单元和夹具壳体。 气体减震器的气体填充方法包括以下步骤：校正管组件和杆导向件的组装位置，夹紧基壳组件; 首先降低气体填充单元，降低杆夹紧单元，降低夹头壳体装置; 使油封脱落，填充气体，次要地降低气体填充单元，同时主要地压缩，并且二次地将基部壳体组件夹紧。 当将气体填充到气体缓冲器的底壳组件中时，该装置和方法不需要在基座壳组件的圆周处冲压用于填充气体的孔。