公开(公告)号：US6058053A

公开(公告)日：2000-05-02

申请号：US195212

申请日：1998-11-18

申请人： Takaharu Tsuji ,  Tsukasa Ooishi ,  Hiroshi Kato ,  Shigeki Tomishima ,  Hiroki Shimano

发明人： Takaharu Tsuji ,  Tsukasa Ooishi ,  Hiroshi Kato ,  Shigeki Tomishima ,  Hiroki Shimano

IPC分类号： G11C29/04 ,  G11C29/00 ,  G11C7/00

CPC分类号： G11C29/84 ,  G11C29/844

摘要： In the semiconductor memory device, independent from redundancy determination by a redundancy determining circuit, a word line activating signal (subdecode signal) for setting a word line in a normal block corresponding to a decoded address signal, is activated. A WL driver includes a driver portion for selecting a word line in the normal block, and a driver portion for selecting a spare word line in a redundant block. When redundancy is not to be used as a result of redundancy determination by the redundancy determining circuit, activated subdecode signal is inactivated. If redundancy is to be used as a result of redundancy determination, a corresponding word line is set to the selected state, using the activated subdecode signal. Thus a semiconductor memory device in which substitution can be done at high speed with high efficiency is provided.

摘要翻译： 在半导体存储器件中，独立于由冗余确定电路进行的冗余确定，激活用于设置与解码的地址信号对应的正常块中的字线的字线激活信号（子代码信号）。 WL驱动器包括用于选择正常块中的字线的驱动器部分和用于在冗余块中选择备用字线的驱动器部分。 作为由冗余确定电路的冗余确定的结果不使用冗余时，激活的子代码信号被去激活。 如果作为冗余确定的结果使用冗余，则使用激活的子代码信号将对应的字线设置为所选择的状态。 因此，提供了可以以高效率高效率地进行替换的半导体存储器件。

公开(公告)号：US5953264A

公开(公告)日：1999-09-14

申请号：US937006

申请日：1997-09-24

申请人： Hiroshige Hirano ,  Hisakazu Kotani ,  Naomi Miyake

发明人： Hiroshige Hirano ,  Hisakazu Kotani ,  Naomi Miyake

IPC分类号： G11C29/00 ,  G11C29/24 ,  G11C13/00

CPC分类号： G11C29/808 ,  G11C29/24 ,  G11C29/812 ,  G11C29/844

摘要： An apparatus for selecting redundant memory cells in integrated circuit memory devices. The apparatus includes eight memory cell blocks, each of which includes a plurality of memory cell groups, a redundant memory cell group of a first set and a redundant memory cell group of a second set; and eight selecting fuse circuit blocks. Four of the selecting fuse circuit blocks are coupled to the memory cell blocks and adapted to select a redundant word line group of the first set of any of the eight memory cell blocks, and the other four selecting fuse circuit blocks are coupled to the memory cell blocks and adapted to select a redundant word line group of the second set of any of the eight memory cell blocks.

摘要翻译： 一种用于在集成电路存储器件中选择冗余存储单元的装置。 该装置包括八个存储单元块，每个存储单元块包括多个存储单元组，第一组的冗余存储单元组和第二组的冗余存储单元组; 和八个选择熔丝电路块。 选择熔丝电路块中的四个耦合到存储单元块并且适于选择八个存储单元块中的任一个的第一组的冗余字线组，而另外四个选择熔丝电路块耦合到存储单元 并且适于选择八个存储器单元块中的任何一个的第二组的冗余字线组。

公开(公告)号：US5920515A

公开(公告)日：1999-07-06

申请号：US938062

申请日：1997-09-26

申请人： Imtiaz P. Shaik ,  Dennis L. Wendell ,  Benjamin S. Wong ,  John C. Holst ,  Donald A. Draper ,  Amos Ben-Meir ,  John G. Favor

发明人： Imtiaz P. Shaik ,  Dennis L. Wendell ,  Benjamin S. Wong ,  John C. Holst ,  Donald A. Draper ,  Amos Ben-Meir ,  John G. Favor

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/84 ,  G11C29/844

摘要： A semiconductor memory array with Built-in Self-Repair (BISR) includes redundancy circuits associated with failed row address stores to drive redundant row word lines, thereby obviating the supply and normal decoding of a substitute addresses. NOT comparator logic compares a failed row address generated and stored by BISR circuits to a row address supplied to the memory array. A TRUE comparator configured in parallel with the NOT comparator simultaneously compares defective row address signal to the supplied row address. Since NOT comparison is performed quickly in dynamic logic without setup and hold time constraints, timing impact on a normal (non-redundant) row decode path is negligible, and since TRUE comparison, though potentially slower than NOT comparison, itself identifies a redundant row address and therefore need not employ an N-bit address to selected word-line decode, redundant row addressing is rapid and does not adversely degrade performance of a self-repaired semiconductor memory array. By providing redundancy handling at the predecode circuit level, rather than at a preliminary address substitution stage, access times to a BISR memory array in accordance with the present invention are improved.

摘要翻译： 具有内置自修复（BISR）的半导体存储器阵列包括与故障行地址存储相关联的冗余电路以驱动冗余行字线，从而避免替代地址的供应和正常解码。 NOT比较器逻辑将由BISR电路生成和存储的故障行地址与提供给存储器阵列的行地址进行比较。 与NOT比较并行配置的TRUE比较器同时将缺陷行地址信号与提供的行地址进行比较。 由于在没有设置和保持时间约束的情况下，在动态逻辑中不快速执行比较，所以对正常（非冗余）行解码路径的定时影响是可以忽略的，并且由于真正的比较虽然潜在地比NOT比较慢，但是它自身识别冗余行地址 因此不需要对所选字线解码采用N位地址，冗余行寻址是快速的并且不会不利地降低自修复的半导体存储器阵列的性能。 通过在预解码电路级提供冗余处理，而不是在初始地址替换阶段，改进了根据本发明的BISR存储器阵列的访问时间。

公开(公告)号：US5905681A

公开(公告)日：1999-05-18

申请号：US876293

申请日：1997-06-16

申请人： Yoshinori Matsui

发明人： Yoshinori Matsui

IPC分类号： G11C11/408 ,  G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/84 ,  G11C29/844 ,  G11C29/785 ,  G11C7/1018

摘要： The redundancy decoder circuit is capable of receipt of burst length information of address signals for first reading out an address of two addresses to be multi-selected and also judging address to be substituted in accordance with other address to be concurrently read out by means of switching, by the burst length signal, the combination logic of the lower bits of the address already prepared.

摘要翻译： 冗余解码器电路能够接收地址信号的突发长度信息，用于首先读出要被多次选择的两个地址的地址，并且还根据要通过切换同时读出的其他地址来判断要被替换的地址 ，通过突发长度信号，已经准备好的地址的低位的组合逻辑。