公开(公告)号：US20060026158A1

公开(公告)日：2006-02-02

申请号：US11160920

申请日：2005-07-15

Applicant: Chia-Jung Hsu

Inventor： Chia-Jung Hsu

IPC: G06F7/00 ,  G06F12/00

CPC classification number: B60S1/40 ,  B60S1/42 ,  G06F7/22

Abstract: The present invention discloses a sorting method using a memory as an auxiliary tool to sort a plurality of items stored in a storage device. The method includes the following steps: (a) retrieving full information of an item to be sorted from the storage device; (b) comparing only partial information of the item to be sorted with partial information of at least one already sorted item stored in the memory to determine an order of the item to be sorted and the already sorted items; and (c) storing partial information of the already sorted items and partial information of the item to be sorted into the memory according to the determined order.

Abstract translation: 本发明公开了一种使用存储器作为辅助工具对存储在存储装置中的多个物品进行分类的排序方法。 该方法包括以下步骤：（a）从存储设备检索待分类物品的完整信息; （b）仅将要分类的项目的部分信息与存储在存储器中的至少一个已经排序的项目的部分信息进行比较，以确定要排序的项目的顺序和已排序的项目; 以及（c）根据确定的顺序将已经排序的项目的部分信息和要分类的项目的部分信息存储到存储器中。

公开(公告)号：US5787426A

公开(公告)日：1998-07-28

申请号：US408304

申请日：1995-03-22

Applicant: Takeshi Koshiba ,  Yasubumi Sakakibara

Inventor： Takeshi Koshiba ,  Yasubumi Sakakibara

IPC: G06F17/30 ,  G06F7/22

CPC classification number: G06F7/22 ,  Y10S707/99933 ,  Y10S707/99935 ,  Y10S707/99937

Abstract: Derivatives representing character string candidates are created from a list of examples of character data. The sorting attribute of the derivatives representing character string candidate is evaluated relating to each example of the character data and a derivatives representing character string is labeled to an internal node. At the same time, the sorting attribute of the derivatives representing character string selected is evaluated relating to each example of the character data to thereby successively sort the example of each character data and create a data sorting tree. New character data is sorted using the data sorting tree. On the other hand, a thesaurus of desired character data is automatically created as a word linked to the derivatives representing character string which is labeled to each internal node present on a path extending along the data sorting tree, or as a word linked to a negative of the derivative representing character string.

Abstract translation: 从字符数据的例子列表中创建表示字符串候选的衍生物。 评估与字符数据的每个示例相关的表示字符串候选的导数的排序属性，并将表示字符串的导数标记到内部节点。 同时，对与字符数据的每一个示例相关的是评估代表所选择的字符串的导数的排序属性，从而连续分类每个字符数据的示例并创建数据排序树。 使用数据排序树对新的字符数据进行排序。 另一方面，所需字符数据的词库被自动创建为链接到代表字符串的衍生词，该字符串被标注到沿着数据分类树延伸的路径上存在的每个内部节点，或者作为与否 的代表字符串的导数。

公开(公告)号：US5764854A

公开(公告)日：1998-06-09

申请号：US490967

申请日：1995-06-15

Applicant: Ken Ota ,  William C. Archibald

Inventor： Ken Ota ,  William C. Archibald

IPC: G06F7/22 ,  G06N7/04 ,  G06F15/18

CPC classification number: G06F9/30021 ,  G06F7/22 ,  G06N7/04

Abstract: A minimum-maximum computation circuit (5) includes a circuit (10) for detecting an order of magnitude of the input label's grades and a circuit for executing a minimum-maximum calculation (41, 42, and 49) according to an order of the magnitude of the input label's grades. The minimum-maximum computation circuit includes a rule memory (20) for storing rule-associative-bit-groups which include a valid/invalid bit for each of the coded rules. Each of the coded rules include an arrangement of valid/invalid bits for indicating whether each of said input labels is included or not in the antecedent of said each of rules. The minimum-maximum computing circuit further includes a weighting factor circuit (63) for providing weighting factors in their magnitude order to be applied to selected fuzzy rules.

Abstract translation: 最小最大计算电路（5）包括用于检测输入标签牌号的数量级的电路（10）和用于执行最小最大计算（41,42和49）的电路， 输入标签牌号的大小。 最小最大计算电路包括用于存储规则关联位组的规则存储器（20），其包括每个编码规则的有效/无效位。 每个编码规则包括有效/无效位的排列，用于指示在所述每个规则的前提中是否包括所述输入标签中的每一个。 最小最大计算电路还包括加权因子电路（63），用于以其幅度顺序提供要应用于所选择的模糊规则的加权因子。

公开(公告)号：US4210961B1

公开(公告)日：1996-10-01

申请号：US94369578

申请日：1978-09-19

Applicant: SYNCSORT INC

Inventor： WHITLOW DUANE L ,  SASSON AZRA

IPC: G06F7/22 ,  G06F7/36

CPC classification number: G06F7/22 ,  Y10S707/99937

公开(公告)号：US5337410A

公开(公告)日：1994-08-09

申请号：US060478

申请日：1993-05-11

Applicant: Peter C. Appel

Inventor： Peter C. Appel

IPC: G06F9/38 ,  G06F7/22 ,  G06F11/267 ,  G06F15/16 ,  G06F15/80 ,  G06T1/20 ,  G09G5/42 ,  G06F15/62

CPC classification number: G06F11/221 ,  G06F7/22 ,  G09G5/42

Abstract: A method and apparatus for merging command/data packets from a plurality of parallel processing units into a concentrated data stream, while also providing for pipeline attribute data storage, direct user access to the pipeline, redirection of the pipeline, data insertion into the pipeline and pipeline diagnostics. The data from a plurality of parallel processing units is recombined in the same order as originally transmitted and then inputted into a buffer for entry into the pipeline. Attribute switching commands are deciphered by the concentrator of the invention and selectively stored and retrieved from the pipeline. New attribute values are passed downstream on command when they are different from existing attributes, or conversely, the concentrator may be overridden by the user so that attribute values supplied by the user may be stored and passed downstream. This technique thus minimizes repetitiveness in attribute switching. Further diagnostics capabilities are provided whereby a user of the graphics processing system is given the ability to plug the pipeline and independently check different data sources and destinations to see if they are functioning properly. This process is further enhanced by the capability of the invention to check the status of each of the concentrator elements in parallel to determine if they are ready before performing any data transfer.

Abstract translation: 一种用于将来自多个并行处理单元的命令/数据分组合并成集中数据流的方法和装置，同时还提供流水线属性数据存储，直接用户对流水线的访问，流水线的重定向，数据插入到流水线中， 管道诊断。 来自多个并行处理单元的数据以与原始发送的顺序重新组合，然后输入到用于进入流水线的缓冲器中。 属性切换命令由本发明的集中器解密，并从管道中选择性地存储和检索。 当新的属性值与现有属性不同时，新的属性值将在命令下游传递，或者相反，该集中器可能被用户覆盖，以便用户提供的属性值可以被存储并传递到下游。 因此，这种技术最小化了属性切换的重复性。 提供了进一步的诊断功能，使图形处理系统的用户能够插入流水线并且独立地检查不同的数据源和目的地以查看它们是否正常工作。 通过本发明能够并行地检查每个集中器元件的状态以确定它们在执行任何数据传输之前是否准备就能进一步增强该过程。

公开(公告)号：US4959771A

公开(公告)日：1990-09-25

申请号：US407693

申请日：1989-09-14

Applicant: Joseph L. Ardini, Jr. ,  Steven Small

Inventor： Joseph L. Ardini, Jr. ,  Steven Small

IPC: G06F5/06 ,  G06F7/22 ,  G06F12/08

CPC classification number: G06F12/0802 ,  G06F5/065 ,  G06F7/22

Abstract: The invention comprises a write buffer system which provides residence time information that increases the merge potential and enhances the write collapse feature of a "smart" buffer. The write buffer has multiple buffer locations for storing data received from a central processor, a data merger for merging data designated by the central processor for subsequent storage in contiguous memory locations, and a write controller for selectively writing the data from the plurality of write buffer locations to the memory. The system further includes time stamp registers in communication with the write controller for storing and updating a time signal representative of the write buffer location having most recently received data. The controller is responsive in part to the time signal, and inhibits the writing to memory of the data in the write buffer location having most recently received data since this is the location most likely to be eligible for a data merge. This feature decreases the number of interruptions to the CPU for data transfer operations.

Abstract translation: 本发明包括写缓冲器系统，其提供增加合并电位并增强“智能”缓冲器的写入折叠特征的停留时间信息。 写缓冲器具有用于存储从中央处理器接收的数据的多个缓冲器位置，用于合并由中央处理器指定的数据的数据合并器，用于在连续存储器位置中随后存储;以及写控制器，用于选择性地从多个写缓冲器中写入数据 位置到内存 该系统还包括与写入控制器通信的时间戳寄存器，用于存储和更新表示具有最近接收的数据的写入缓冲器位置的时间信号。 控制器部分地响应于时间信号，并且禁止对具有最近接收的数据的写缓冲器位置中的数据的存储器的写入，因为这是最有可能符合数据合并的位置。 此功能可减少CPU对数据传输操作的中断次数。

公开(公告)号：US4958141A

公开(公告)日：1990-09-18

申请号：US220138

申请日：1988-07-15

Applicant: Ronald L. Engelsman

Inventor： Ronald L. Engelsman

IPC: G06F7/22

CPC classification number: G06F7/22

Abstract: A ranking circuit operable in real time to rank a set of periodically changing sample values, having a series of sequentially clocked storage registers for sequentially storing the sample values, a series of corresponding first comparators for comparing each sample stored to the incoming sample, a summer for summing the outputs of the first comparators to assign an initial rank to the incoming sample, a series of rank registers for storing the initial rank value and a rank value corresponding to each sample in the sample registers, increment/decrement logic for adjusting each rank in the respective rank registers as each new sample is received, logic for effectively excluding a target sample from the ranking process, and logic for outputting a sample value of selected rank during each clock cycle. Optional logic for automatically adjusting the selected rank based on the relative amplitudes of the samples being ranked is also disclosed.

Abstract translation: 一种可实时操作的排序电路，用于对一组周期性变化的采样值进行排序，具有一系列顺序存储的存储寄存器用于顺序存储采样值，一系列相应的第一比较器，用于比较存储到输入采样的每个样本，夏季 为了对第一比较器的输出求和以对入局样本分配初始等级，一系列用于存储初始秩值的秩寄存器和与采样寄存器中的每个采样相对应的等级值，用于调整每个等级的递增/递减逻辑 在接收到每个新样本的各个等级寄存器中，用于从排序处理中有效地排除目标样本的逻辑，以及用于在每个时钟周期期间输出所选择的等级的采样值的逻辑。 还公开了用于基于被评级的样本的相对幅度自动调整所选等级的可选逻辑。

公开(公告)号：US4498189A

公开(公告)日：1985-02-05

申请号：US350037

申请日：1982-02-18

Applicant: Nobuhiko Mori

Inventor： Nobuhiko Mori

IPC: G06K9/62 ,  G06F7/22 ,  G06K9/64

CPC classification number: G06F9/30021 ,  G06F7/22 ,  G06K9/6202 ,  G06K9/64

Abstract: In a pattern matching method, the input pattern of a character is compared with each of a plurality of standard patterns to detect similarities and differences by counting the number of pattern elements which are or are not matched with each other. To do this, a high-speed comparator stores a plurality of comparing data in a memory, which is driven by a clock pulse train. The memory produces a plurality of sequence signals during each time interval when the clock pulses of a number responding to a plurality of comparing data are applied thereto. The first or last produced sequence signal is detected from among the plurality of sequence signals and is used to extract the maximum or minimum data.

Abstract translation: 在图案匹配方法中，将字符的输入图案与多个标准图案中的每一个进行比较，以通过对彼此匹配或不匹配的图案元素的数量进行计数来检测相似和差异。 为此，高速比较器将多个比较数据存储在由时钟脉冲串驱动的存储器中。 当将响应于多个比较数据的数字的时钟脉冲施加到其上时，存储器在每个时间间隔期间产生多个序列信号。 从多个序列信号中检测第一或最后产生的序列信号，并且用于提取最大或最小数据。

公开(公告)号：US4497039A

公开(公告)日：1985-01-29

申请号：US393558

申请日：1982-06-30

Applicant: Hazime Kitakami ,  Hiroshi Ishikawa ,  Masayoshi Tezuka ,  Susumu Adachi ,  Akifumi Makinouchi

Inventor： Hazime Kitakami ,  Hiroshi Ishikawa ,  Masayoshi Tezuka ,  Susumu Adachi ,  Akifumi Makinouchi

IPC: G06F12/00 ,  G06F7/22 ,  G06F17/30 ,  G06F15/20

CPC classification number: G06F17/30501 ,  G06F17/30498 ,  G06F7/22 ,  Y10S707/99932 ,  Y10S707/99937

Abstract: The present invention discloses a join operation processing system in a relational model where a data base processing mechanism provides at least maximum/minimum calculation execution means, reduction sort execution means and the join operation execution means.During the join operation for generating a new table linking tuples of a plurality of pertinent tables based on a common field or plurality of common fields, a minimum extraction range for determining the tuples to be processed is determined with respect to the join field or the plurality of join fields for each table which is considered as the object of the join. The operation rate is thereby improved by omitting the processing referring to unwanted data.

Abstract translation: 本发明公开了一种关系模型中的连接操作处理系统，其中数据库处理机构至少提供最大/最小计算执行装置，缩减排序执行装置和联合操作执行装置。 在用于生成基于公共字段或多个公共字段来连接多个相关表的元组的新表的联接操作期间，针对连接字段或多个公共字段确定用于确定要被处理的元组的最小提取范围 的每个表的连接字段被认为是连接的对象。 从而通过省略涉及不想要的数据的处理来改善操作速率。

公开(公告)号：US4259719A

公开(公告)日：1981-03-31

申请号：US48201

申请日：1979-06-13

Applicant: Brian S. Edelman ,  Ralph L. Robinson, Jr.

Inventor： Brian S. Edelman ,  Ralph L. Robinson, Jr.

IPC: G05B1/01 ,  F02D41/24 ,  F02D45/00 ,  G05B15/02 ,  G06F7/22 ,  G06F7/78 ,  G06F13/20 ,  G06F15/78 ,  G06F19/00 ,  G06F3/00

CPC classification number: G06F7/78 ,  F02D41/28 ,  G06F13/20 ,  G06F7/22 ,  F02D2250/12

Abstract: A digital computer having a real time counter and a memory/address bus uses binary input data comprising a plurality of bits of information to generate output information in response to a program. The invention provides improved processing of the binary input data. A transition from one state to another of one or more of the bits of binary input data causes a byte of binary input data containing the bit or bits having undergone transition to be placed in an input holding register. Also, the real time at which the transition occurred is placed in a capture-time holding register. The contents of the input holding and capture-time holding registers are repetitively placed in a stack as pending input data bytes. The pending input data bytes are accessible to the computer central processing unit, as required by the program, via the memory/address bus.

Abstract translation: 具有实时计数器和存储器/地址总线的数字计算机使用包括多个位信息的二进制输入数据来响应于程序产生输出信息。 本发明提供二进制输入数据的改进处理。 从二进制输入数据的一个或多个位的一个状态到另一个状态的转变使包含经过转换的位的二进制输入数据的字节被放置在输入保持寄存器中。 而且，发生转换的实时时间被放置在捕获时间保持寄存器中。 将输入保持和捕获时间保持寄存器的内容重复放置在堆栈中作为未决输入数据字节。 根据程序的要求，通过存储器/地址总线，待处理的输入数据字节可由计算机中央处理单元访问。