公开(公告)号：US20240012582A1

公开(公告)日：2024-01-11

申请号：US18370871

申请日：2023-09-20

申请人： Samsung Electronics Co., Ltd.

发明人： Fred WORLEY ,  Harry ROGERS ,  Gunneswara MARRIPUDI ,  Zhan PING ,  Vikas SINHA

IPC分类号： G06F3/06 ,  G06F13/42 ,  G06F13/40

CPC分类号： G06F3/0661 ,  G06F3/0688 ,  G06F13/4282 ,  G06F13/4022 ,  G06F3/0632 ,  G06F3/0658 ,  G06F3/0613 ,  G06F3/0629 ,  G06F3/0683 ,  G06F13/4081

摘要： Embodiments of the inventive concept include solid state drive (SSD) multi-card adapters that can include multiple solid state drive cards, which can be incorporated into existing enterprise servers without major architectural changes, thereby enabling the server industry ecosystem to easily integrate evolving solid state drive technologies into servers. The SSD multi-card adapters can include an interface section between various solid state drive cards and drive connector types. The interface section can perform protocol translation, packet switching and routing, data encryption, data compression, management information aggregation, virtualization, and other functions.

公开(公告)号：US11868665B2

公开(公告)日：2024-01-09

申请号：US17681512

申请日：2022-02-25

申请人： Intel Corporation

发明人： Nilesh N. Shah ,  Chetan Chauhan ,  Shigeki Tomishima ,  Nahid Hassan ,  Andrew Chaang Ling

IPC分类号： G11C13/00 ,  G06F3/06 ,  G06N5/04

CPC分类号： G06F3/0679 ,  G06F3/0613 ,  G06F3/0644 ,  G06N5/04 ,  G11C13/0004 ,  G11C13/0007

摘要： Examples herein relate to a solid state drive that includes a media, first circuitry, and second circuitry. In some examples, the first circuitry is to execute one or more commands. In some examples, the second circuitry is to receive a configuration of at one type of command, where the configuration is to define an amount of media bandwidth allocated for the at one type of command; receive a command; and assign the received command to the first circuitry for execution.

公开(公告)号：US11868660B2

公开(公告)日：2024-01-09

申请号：US17720868

申请日：2022-04-14

申请人： MICRON TECHNOLOGY, INC.

发明人： Muthazhagan Balasubramani ,  Woei Chen Peh

IPC分类号： G06F12/00 ,  G06F3/06

CPC分类号： G06F3/0659 ,  G06F3/0604 ,  G06F3/0613 ,  G06F3/0635 ,  G06F3/0679

摘要： A set of submission queues associated with a host system is identified. A first set of internal queues and a second set of internal queues is generated based on the set of submission queues. Responsive to fetching a first memory access command pending in a submission queue of the set of submission queues, a first internal queue of the first set of internal queues is populated. Responsive to processing the first memory access command from the first internal queue of the first set of internal queues, a second internal queue of the second set of internal queues is populated. Responsive to completion of the first memory access command from the second internal queue of the second set of internal queues, an indication of the completion of the first memory access command is returned to the host system.

公开(公告)号：US11861215B2

公开(公告)日：2024-01-02

申请号：US18189732

申请日：2023-03-24

申请人： JABIL INC.

发明人： Fengquan Zheng

IPC分类号： G06F3/06 ,  G06F13/42

CPC分类号： G06F3/0655 ,  G06F3/0613 ,  G06F3/0688 ,  G06F3/0689 ,  G06F13/4221 ,  G06F13/4282 ,  G06F2213/0026 ,  G06F2213/0028

摘要： An electronics assembly including a plurality of midplanes positioned between and coupled to a plurality of electronic components at one side of the plurality of midplanes and at least one electronic component at an opposite side of the plurality of midplanes in a manner so that the midplanes are vertically oriented in parallel relative to each other so as to define spaces therebetween. The midplanes each include electrical traces configured to send signals among and between the plurality of electronic components at the one side of the midplanes and the at least one electronic component at the opposite side of the midplanes.

公开(公告)号：US20230418473A1

公开(公告)日：2023-12-28

申请号：US17973555

申请日：2022-10-26

申请人： Nuvoton Technology Corporation

发明人： Hung-Wei Chiu

IPC分类号： G06F3/06

CPC分类号： G06F3/0613 ,  G06F3/0629 ,  G06F3/0673

摘要： A continuous memory access acceleration circuit, an address shift circuit, and an address generation method are provided. An arithmetic circuit calculates a memory access address according to temporary data provided by a register circuit. A counter provides a count value. A counting control circuit controls the counter to accumulate the count value according to access times of a memory. An adder circuit adds the memory access address and the count value to generate a target memory access address.

公开(公告)号：US11853589B2

公开(公告)日：2023-12-26

申请号：US18158957

申请日：2023-01-24

申请人： NetApp, Inc.

发明人： Krishna Murthy Chandraiah Setty Narasingarayanapeta ,  Preetham Shenoy ,  Divya Kathiresan ,  Rakesh Bhargava

IPC分类号： G06F3/06

CPC分类号： G06F3/065 ,  G06F3/067 ,  G06F3/0613 ,  G06F3/0619 ,  G06F3/0631 ,  G06F3/0653 ,  G06F3/0659

摘要： Systems and methods are described for performing persistent inflight tracking of operations (Ops) within a cross-site storage solution. According to one embodiment, a method comprises maintaining state information regarding a data synchronous replication status for a first storage object of a primary storage cluster and a second storage object of a secondary storage cluster. The method includes performing persistent inflight tracking of I/O operations with a first Op log of the primary storage cluster and a second Op log of the secondary storage cluster, establishing and comparing Op ranges for the first and second Op logs, and determining a relation between the Op range of the first Op log and the Op range of the second Op log to prevent divergence of Ops in the first and second Op logs and to support parallel split of the Ops.

公开(公告)号：US11853565B2

公开(公告)日：2023-12-26

申请号：US17492224

申请日：2021-10-01

申请人： Western Digital Technologies, Inc.

发明人： Ravishankar Surianarayanan

IPC分类号： G06F3/06

CPC分类号： G06F3/0631 ,  G06F3/064 ,  G06F3/0613 ,  G06F3/0644 ,  G06F3/0652 ,  G06F3/0673

摘要： A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to allocate two or more zones to a first superblock of a plurality of superblocks. The controller is further configured to allocate a zone to a second superblock, where the second superblock only stores data of the zone. The first superblock has a first priority and the second superblock has a second priority, where the second priority is greater than the first priority. Data is moved from the first superblock to another superblock dedicated for a single zone after the first superblock is closed.

公开(公告)号：US20230409205A1

公开(公告)日：2023-12-21

申请号：US18339812

申请日：2023-06-22

申请人： Rambus Inc.

发明人： Aws Shallal ,  Micheal Miller ,  Stephen Horn

IPC分类号： G06F3/06 ,  G11C14/00 ,  G06F12/14 ,  G06F11/00 ,  G11C5/04 ,  G11C11/00 ,  G06F12/0802 ,  G06F13/16

CPC分类号： G06F3/0613 ,  G06F3/0611 ,  G11C14/0009 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/1441 ,  G06F11/00 ,  G11C5/04 ,  G11C11/005 ,  G06F3/065 ,  G06F3/0685 ,  G06F12/0802 ,  G06F13/1673 ,  G06F13/1668 ,  G11C7/1051

摘要： Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.

公开(公告)号：US20230409204A1

公开(公告)日：2023-12-21

申请号：US18230117

申请日：2023-08-03

申请人： XILINX, INC.

发明人： Abhishek Kumar JAIN ,  Henri FRAISSE ,  Dinesh D. GAITONDE

IPC分类号： G06F3/06

CPC分类号： G06F3/0613 ,  G06F3/0659 ,  G06F3/0673

摘要： A method includes receiving a value and an identifier from a first memory and hashing the identifier to produce a memory block identifier. The method also includes routing, based on the memory block identifier, a read request to a memory block of a plurality of memory blocks and updating the value received from the first memory based on a property received from the memory block in response to the read request. The memory further includes storing the updated value in the first memory.

公开(公告)号：US20230409203A1

公开(公告)日：2023-12-21

申请号：US18177673

申请日：2023-03-02

申请人： Kioxia Corporation

发明人： Tadashi AMADA

IPC分类号： G06F3/06

CPC分类号： G06F3/0613 ,  G06F3/0659 ,  G06F3/0679

摘要： A memory system includes a nonvolatile memory and a controller. The controller is configured to determine a first predicted read address as a subsequent read address following an input read address from which data is to be read, based on the input read address and a preset write sequence rule, determine a second predicted read address as the subsequent read address, based on the input read address and a read sequence history, select one of read addresses including the first and second predicted read addresses as a target read address, and read data from the target read address of the nonvolatile memory.