公开(公告)号：US11081447B2

公开(公告)日：2021-08-03

申请号：US16573817

申请日：2019-09-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shin-Yi Yang ,  Yu-Chen Chan ,  Ming-Han Lee ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L23/522

摘要： A semiconductor structure is provided. The semiconductor structure comprises a first conductive feature embedded within a first dielectric layer, a via disposed over the first conductive feature, a second conductive feature disposed over the via, and a graphene layer disposed over at least a portion of the first conductive feature. The via electrically couples the first conductive feature to the second conductive feature.

公开(公告)号：US20210082829A1

公开(公告)日：2021-03-18

申请号：US16571279

申请日：2019-09-16

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shin-Yi Yang ,  Ming-Han Lee ,  Shau-Lin Shue

IPC分类号： H01L23/532 ,  H01L21/324 ,  H01L23/522 ,  H01L21/768

摘要： Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a third dielectric layer over the second dielectric layer, a second contact feature extending through the second dielectric layer and the third dielectric layer, and a graphene layer between the second contact feature and the third dielectric layer.

公开(公告)号：US20210057335A1

公开(公告)日：2021-02-25

申请号：US16547847

申请日：2019-08-22

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shin-Yi Yang ,  Guanyu Luo ,  Chin-Lung Chung ,  Ming-Han Lee ,  Shau-Lin Shue

IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

摘要： Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a second contact feature over the first contact feature, a barrier layer between the second dielectric layer and the second contact feature, and a graphene layer between the second contact feature and the first contact feature.

公开(公告)号：US20200312708A1

公开(公告)日：2020-10-01

申请号：US16712430

申请日：2019-12-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Kang Fu ,  Ming-Han Lee ,  Shau-Lin Shue

IPC分类号： H01L21/768 ,  H01L21/321 ,  H01L23/532 ,  H01L23/535

摘要： A method of forming a semiconductor structure includes removing a top portion of a conductive feature disposed in a first dielectric layer and over a semiconductor substrate to form a first recess, depositing a second dielectric layer over the first dielectric layer, where the second dielectric layer includes a first region disposed vertically above the first recess and a second region disposed adjacent the first region, and forming a third dielectric layer over the second dielectric layer. The method further includes subsequently forming openings in the third dielectric layer that extend to expose the second dielectric layer, depositing a conductive material in the openings, and planarizing the conductive material to form conductive features in the first and the second regions, where the planarizing completely removes portions of the third dielectric layer disposed in the second region.

公开(公告)号：US10763211B2

公开(公告)日：2020-09-01

申请号：US16048921

申请日：2018-07-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Ming-Han Lee ,  Shau-Lin Shue

IPC分类号： H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522

摘要： A semiconductor device includes a first interlayer dielectric (ILD) layer disposed over a substrate, and a first metal wiring pattern formed in the first interlayer dielectric layer and extending in a first direction parallel with the substrate. In a cross section along a second direction which crosses the first direction and is in parallel with the substrate, a top of the first metal wiring pattern is covered by a first two-dimensional material layer.

公开(公告)号：US10741493B2

公开(公告)日：2020-08-11

申请号：US16200076

申请日：2018-11-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yu-Chen Chan ,  Shin-Yi Yang ,  Ming-Han Lee

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L21/285

摘要： A structure includes a non-insulator structure, an etch stop layer, a dielectric layer, a conductive feature, and a first diffusion barrier layer. The etch stop layer is over the non-insulator structure. The dielectric layer is over the etch stop layer. The conductive feature is in the dielectric layer. The first diffusion barrier layer wraps around the conductive feature, the first diffusion barrier layer has a base portion between the non-insulator structure and the conductive feature, and the first diffusion barrier layer has a lateral extension from the base portion of the first diffusion barrier layer.

公开(公告)号：US20200098685A1

公开(公告)日：2020-03-26

申请号：US16534411

申请日：2019-08-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ming-Han Lee ,  Shau-Lin Shue

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/321 ,  H01L23/532 ,  H01L23/528 ,  H01L21/311 ,  H01L21/027

摘要： A method of fabricating a semiconductor interconnect structure includes forming a via in a dielectric layer, depositing a ruthenium-containing conductive layer over a top surface of the via and a top surface of the dielectric layer, and patterning the ruthenium-containing conductive layer to form a conductive line over the top surface of the via, where a thickness of the conductive line is less than a thickness of the via.

公开(公告)号：US10510657B2

公开(公告)日：2019-12-17

申请号：US15715327

申请日：2017-09-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Shin-Yi Yang ,  Ming-Han Lee ,  Shau-Lin Shue

IPC分类号： H01L23/522

摘要： A semiconductor device includes a substrate, a dielectric layer, a via, a line, and a capping layer. The substrate includes at least one conductive layer, in which a top surface of the at least one conductive layer has a first portion and a second portion. The dielectric layer is disposed on the substrate and the first portion of the top surface of the at least one conductive layer. The via is disposed in the dielectric layer on the second portion of the top surface of the at least one conductive layer. The line is disposed on the via and a portion of the dielectric layer. The capping layer is disposed on a top surface of the line and peripherally encloses a side surface of the line, in which the capping layer has an etch selectivity with respect to the line.

公开(公告)号：US10453740B2

公开(公告)日：2019-10-22

申请号：US15679385

申请日：2017-08-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tz-Jun Kuo ,  Chien-Hsin Ho ,  Ming-Han Lee

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532

摘要： Embodiments and methods of an interconnect structure are provided. The interconnect structure includes a via, a trench that has an overlapping area with a top of the via, and a first layer of conducting material that has an overlapping area with a bottom of the via. The interconnect also includes a second layer of conducting material formed in the via, and a third layer of conducting material formed in the trench. The second layer of conducting material is in contact with the first layer of conducting material without a barrier in between the two conducting materials. The absence of the barrier at the bottom of the via can reduce the contact resistance of the interconnect structure.

公开(公告)号：US10163700B2

公开(公告)日：2018-12-25

申请号：US14989036

申请日：2016-01-06

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Kang Fu ,  Ming-Han Lee

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/06 ,  H01L21/3105 ,  H01L21/321

摘要： Semiconductor structures and methods for forming the same are provided. The method for manufacturing a semiconductor structure includes forming a dielectric layer over a substrate and forming a sacrificial layer over the dielectric layer. The method for manufacturing a semiconductor structure further includes forming a trench through the sacrificial layer and the dielectric layer and forming a conductive structure in the trench. The method for manufacturing a semiconductor structure further includes removing the sacrificial layer. In addition, a top surface of the conductive feature is not level with a top surface of the dielectric layer after the sacrificial layer is removed.