公开(公告)号：US09992512B2

公开(公告)日：2018-06-05

申请号：US14872147

申请日：2015-10-01

Applicant: MEDIATEK INC.

Inventor： Shun-Hsiang Chuang ,  Chih-Ming Wang ,  Yung-Chang Chang

IPC: H04N19/577 ,  H04N19/176 ,  H04N19/105 ,  H04N19/52 ,  H04N19/96 ,  H04N19/58

CPC classification number: H04N19/577 ,  H04N19/105 ,  H04N19/176 ,  H04N19/52 ,  H04N19/58 ,  H04N19/96

Abstract: A method for motion vector predictor derivation of a block includes following steps: during a same-reference-frame stage of the motion vector predictor derivation, scanning a plurality of candidate motion vector predictors derived from neighbors of the block, and generating a determination result by determining if any candidate motion vector predictor is qualified for a different-reference-frame stage of the motion vector predictor derivation; and referring to the determination result to selectively enable the different-reference-frame stage following the same-reference-frame stage.

公开(公告)号：US09973748B1

公开(公告)日：2018-05-15

申请号：US14259144

申请日：2014-04-22

Applicant: MEDIATEK INC.

Inventor： Chia-Yun Cheng ,  Yung-Chang Chang

IPC: H04N19/00 ,  H04N19/136 ,  H04N19/127 ,  H04N19/119 ,  H04N19/176 ,  H04N19/196

CPC classification number: H04N19/00139 ,  H04N19/00 ,  H04N19/00072 ,  H04N19/00103 ,  H04N19/00278 ,  H04N19/00369

Abstract: A multi-core video decoder system has a syntax parser, a storage device, a plurality of video decoder cores and a control unit. The syntax parser performs syntax parsing upon an incoming encoded video bitstream to derive required information of each picture to be decoded. The storage device buffers the required information of each picture. The control unit controls the video decoder cores to load required information of a plurality of coding rows in a picture from the storage device and then decode the coding rows in the picture, respectively.

公开(公告)号：US09965021B2

公开(公告)日：2018-05-08

申请号：US14745509

申请日：2015-06-22

Applicant: MediaTek Inc.

Inventor： Chih-Ming Wang ,  Yung-Chang Chang

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3206 ,  Y02D10/171 ,  Y02D50/20

Abstract: A power management method is provided to detect system information for a multimedia process, which is to be executed in a multimedia processor system that includes a plurality of cores belonging to a plurality of power domains. The power domains are controlled independently of one another. The method further identifies a set of power domains that provides a processing capacity matching a requirement of the multimedia process indicated in the system information, and supplies power to one or more of the power domains according to the identified set of power domains.

公开(公告)号：US20180124427A1

公开(公告)日：2018-05-03

申请号：US15860688

申请日：2018-01-03

Applicant: MEDIATEK INC.

Inventor： Shun-Hsiang Chuang ,  Chih-Ming Wang ,  Yung-Chang Chang

IPC: H04N19/593 ,  H04N19/119 ,  H04N19/52 ,  H04N19/176

CPC classification number: H04N19/593 ,  H04N19/119 ,  H04N19/176 ,  H04N19/52

Abstract: An exemplary motion vector predictor determination method includes the following steps: determining a motion vector predictor of a block according to motion vector data of neighbor units associated with the block; and utilizing a motion vector predictor computing circuit for assigning the motion vector predictor determined for the block to a first sub-block within the block. In addition, an exemplary motion vector predictor determination apparatus employing the exemplary motion vector predictor determination method is provided.

公开(公告)号：US20170244981A1

公开(公告)日：2017-08-24

申请号：US15439947

申请日：2017-02-23

Applicant: MEDIATEK INC.

Inventor： Chi-Hung Chen ,  Yung-Chang Chang ,  Chih-Ming Wang

IPC: H04N19/82 ,  H04N19/176 ,  H04N19/59 ,  H04N19/182

CPC classification number: H04N19/82 ,  H04N19/117 ,  H04N19/176 ,  H04N19/182 ,  H04N19/523 ,  H04N19/59

Abstract: A reconfigurable interpolation filter has an L×1 parallelism integer pixel and sub-integer pixel processing filter and a filter configuration circuit. The L×1 parallelism integer pixel and sub-integer pixel processing filter calculates L filtered samples at a same pixel line in a parallel fashion, wherein L is a positive integer not smaller than one. The filter configuration circuit reconfigures the L×1 parallelism integer pixel and sub-integer pixel processing filter into an (L/M)×M parallelism integer pixel and sub-integer pixel processing filter according to a width of a prediction block. The (L/M)×M parallelism integer pixel and sub-integer pixel processing filter processes the prediction block by calculating L/M filtered samples at each of M pixel lines in a parallel fashion, wherein M is a positive integer not smaller than one, and L/M is a positive integer.

公开(公告)号：US09648144B2

公开(公告)日：2017-05-09

申请号：US14546213

申请日：2014-11-18

Applicant: MediaTek Inc.

Inventor： Chi-Cheng Ju ,  Chia-Yun Cheng ,  Yung-Chang Chang ,  Chih-Ming Wang

IPC: H04L29/06 ,  H03M7/30

CPC classification number: H04L69/04 ,  H03M7/3059 ,  H04L69/22

Abstract: A transmitter device includes a processing unit and a compression unit. The processing unit obtains a branch of data and partitions the branch of data into a plurality of snippets. Each snippet includes a group of data. The compression unit compresses each snippet into a plurality of packets according to value of each datum included in the corresponding snippet. The compression unit compares the value of each datum with a first threshold value to generate a first packet. The first packet includes first information indicating which data included in the corresponding snippet has the corresponding value not equal to the first threshold value. The compression unit further generates the remaining packets according to the first information.

公开(公告)号：US09565418B2

公开(公告)日：2017-02-07

申请号：US14035962

申请日：2013-09-25

Applicant: MEDIATEK INC.

Inventor： Te-Chi Hsiao ,  Yung-Chang Chang ,  Ching-Chieh Wang ,  Shih-Hung Lin ,  Chi-Cheng Ju

IPC: H04N7/18 ,  H04N13/00 ,  H04N21/2343 ,  H04N19/597 ,  H04N19/44 ,  H04N19/30

CPC classification number: H04N13/161 ,  H04N19/30 ,  H04N19/44 ,  H04N19/597 ,  H04N21/234327

Abstract: An exemplary decoding method of an input video bitstream including a first bitstream and a second bitstream includes: decoding a first picture in the first bitstream; after a required decoded data derived from decoding the first picture is ready for a first decoding operation of a second picture in the first bitstream, performing the first decoding operation; and after a required decoded data derived from decoding the first picture is ready for a second decoding operation of a picture in the second bitstream, performing the second decoding operation, wherein a time period of decoding the second picture in the first bitstream and a time period of decoding the picture in the second bitstream are overlapped in time.

Abstract translation: 包括第一比特流和第二比特流的输入视频比特流的示例性解码方法包括：对第一比特流中的第一图像进行解码; 在从第一图像解码得到的所需解码数据准备好进行第一比特流中的第二图像的第一解码操作之后，执行第一解码操作; 并且在从第一图像的解码得到的所需解码数据准备好进行第二比特流中的图像的第二解码操作之后，执行第二解码操作，其中对第一比特流中的第二图像进行解码的时间段和时间段 对第二位流中的图像进行解码的时间重叠。

公开(公告)号：US20170026648A1

公开(公告)日：2017-01-26

申请号：US15209774

申请日：2016-07-14

Applicant: MEDIATEK INC.

Inventor： Ming-Long Wu ,  Sheng-Jen Wang ,  Chia-Yun Cheng ,  Yu-Cheng Chu ,  Hao-Chun Chung ,  Shen-Kai Chang ,  Yung-Chang Chang

IPC: H04N19/13 ,  H04N19/44 ,  H04N19/42 ,  H04N19/176

CPC classification number: H04N19/13 ,  H04N19/46

Abstract: A hybrid video decoder has a hardware decoding circuit, a software decoding circuit, and a meta-data access system. The hardware decoding circuit deals with a first portion of a video decoding process for at least a portion of a frame, wherein the first portion of the video decoding process includes entropy decoding. The software decoding circuit deals with a second portion of the video decoding process. The meta-data access system manages meta data transferred between the hardware decoding circuit and the software decoding circuit.

Abstract translation: 混合视频解码器具有硬件解码电路，软件解码电路和元数据访问系统。 硬件解码电路处理帧的至少一部分的视频解码处理的第一部分，其中视频解码处理的第一部分包括熵解码。 软件解码电路处理视频解码过程的第二部分。 元数据访问系统管理在硬件解码电路和软件解码电路之间传送的元数据。

公开(公告)号：US20160241863A1

公开(公告)日：2016-08-18

申请号：US15028717

申请日：2015-09-17

Applicant: MEDIATEK INC.

Inventor： Ming-Long Wu ,  Chia-Yun Cheng ,  Yung-Chang Chang

IPC: H04N19/436 ,  H04N19/172 ,  H04N19/174 ,  H04N19/91 ,  H04N19/44 ,  H04N19/593 ,  H04N19/70 ,  H04N19/127 ,  H04N19/184

CPC classification number: H04N19/436 ,  H04N19/127 ,  H04N19/172 ,  H04N19/174 ,  H04N19/184 ,  H04N19/44 ,  H04N19/593 ,  H04N19/70 ,  H04N19/91

Abstract: A syntax parsing apparatus includes a plurality of syntax parsing circuits and a dispatcher. Each of the syntax parsing circuits has at least entropy decoding capability. The syntax parsing circuits generate a plurality of entropy decoding results of a plurality of image regions within a same frame, respectively. The dispatcher assigns bitstream start points of the image regions to the syntax parsing circuits, and triggers the syntax parsing circuits to start entropy decoding, respectively.

Abstract translation: 语法解析装置包括多个语法解析电路和调度器。 每个语法解析电路至少具有熵解码能力。 语法解析电路分别在同一帧内产生多个图像区域的多个熵解码结果。 调度员将图像区域的位流起始点分配给语法解析电路，并分别触发语法解析电路以开始熵解码。

公开(公告)号：US20160227240A1

公开(公告)日：2016-08-04

申请号：US15007232

申请日：2016-01-27

Applicant: MEDIATEK INC.

Inventor： Min-Hao Chiu ,  Yung-Chang Chang

IPC: H04N19/44 ,  H04N19/423 ,  H04N19/70

CPC classification number: H04N19/70 ,  H04N19/12

Abstract: A video decoder has a first processing circuit and a second processing circuit. A shared storage device is accessible to the first processing circuit and the second processing circuit. The first processing circuit performs a first decoding operation according to data access of the shared storage device. The second processing circuit performs a second decoding operation according to data access of the shared storage device. The first decoding operation is at least a portion of a first decoding function complying with a first video coding standard, and the second decoding operation is at least a portion of a second decoding function complying with a second video coding standard different from the first video coding standard.

Abstract translation: 视频解码器具有第一处理电路和第二处理电路。 共享存储设备可由第一处理电路和第二处理电路访问。 第一处理电路根据共享存储装置的数据访问执行第一解码操作。 第二处理电路根据共享存储装置的数据访问执行第二解码操作。 第一解码操作是符合第一视频编码标准的第一解码功能的至少一部分，并且第二解码操作是符合与第一视频编码不同的第二视频编码标准的第二解码功能的至少一部分 标准。