公开(公告)号：US09484465B2

公开(公告)日：2016-11-01

申请号：US14374987

申请日：2013-12-09

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Hyun Sic Choi ,  Hui Li ,  Zhiqiang Xu ,  Yoon Sung Um

IPC: G02F1/1343 ,  H01L29/786 ,  H01L27/12 ,  H01L29/417 ,  G02F1/1368 ,  G02F1/1362

CPC classification number: H01L29/78648 ,  G02F1/134363 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2001/134372 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/78633

Abstract: A array substrate is disclosed. The array substrate includes: a substrate (10); and a first gate metal layer (111), a first gate insulating layer (121), a semiconductor layer (13) and a source-drain electrode layer (14) disposed in this order on the substrate from bottom to top. The array substrate (10) further includes a second gate insulating layer (122) disposed on the source-drain electrode layer (14); and a second gate metal layer (112) disposed on the second gate insulating layer (122). A method of manufacturing an array substrate is also disclosed.

Abstract translation: 公开了阵列基板。 阵列基板包括：基板（10）; 以及从底部到顶部依次设置在基板上的第一栅极金属层（111），第一栅极绝缘层（121），半导体层（13）和源极 - 漏极电极层（14）。 阵列基板（10）还包括设置在源极 - 漏极电极层（14）上的第二栅极绝缘层（122）。 和设置在第二栅极绝缘层（122）上的第二栅极金属层（112）。 还公开了阵列基板的制造方法。

公开(公告)号：US09477016B2

公开(公告)日：2016-10-25

申请号：US14106976

申请日：2013-12-16

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Hui Li ,  Hyunsic Choi ,  Yoonsung Um ,  Zhiqiang Xu

IPC: G02B5/04 ,  G02B5/30 ,  G02F1/1335 ,  G02F1/1333

CPC classification number: G02B5/04 ,  G02B5/3025 ,  G02F1/13336 ,  G02F1/133524 ,  G02F1/133528 ,  G02F1/133536 ,  G02F1/133553 ,  G02F2001/133538 ,  G02F2001/133562

Abstract: A display includes an effective display area and a frame area; an image overlap display area is disposed at a position in the effective display area, close to the frame area, and includes first display positions related to an image to be displayed in the effective display area and second display positions related to an image to be displayed in the frame area; the first and second display positions are distributed in an alternate form; a polarization splitting prism is disposed on a light-emitting surface of the display and at a position at least corresponding to the frame area and the image overlap display area; and a convergent prism configured to converge light from the second display positions in the image overlap display area to the frame area is disposed on a light-emitting surface of the polarization splitting prism. Also a tiled display is disclosed.

Abstract translation: 显示器包括有效显示区域和帧区域; 图像重叠显示区域设置在有效显示区域中靠近帧区域的位置处，并且包括与要显示在有效显示区域中的图像相关的第一显示位置和与要显示的图像相关的第二显示位置 在框架区域; 第一和第二显示位置以另一种形式分布; 偏振分束棱镜被布置在显示器的发光表面上并且至少对应于帧区域和图像重叠显示区域的位置; 并且配置成将来自图像重叠显示区域中的第二显示位置的光会聚到帧区域的会聚棱镜设置在偏振分束棱镜的发光表面上。 还公开了一种平铺显示器。

公开(公告)号：US08877649B2

公开(公告)日：2014-11-04

申请号：US13991724

申请日：2012-12-13

Applicant: Boe Technology Group Co., Ltd.

Inventor： Hyun Sic Choi ,  Zhiqiang Xu ,  Hui Li

IPC: H01L21/311 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  G02F1/1362 ,  G02F1/1339 ,  G02F1/1337

CPC classification number: H01L23/544 ,  G02F1/133711 ,  G02F1/13394 ,  G02F1/136227 ,  G02F2001/136236 ,  H01L21/76802 ,  H01L27/1214 ,  H01L27/1248 ,  H01L27/1288 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention disclose a thin film transistor array substrate, a method of manufacturing the same, and display device. A method of manufacturing a thin film transistor array substrate, comprises: forming a resin layer on a substrate formed with a thin film transistor array, patterning the resin layer by using a mask process to form a spacer and a contact hole filling layer, the contact hole filing layer is used for filling contact holes on the thin film transistor array substrate; forming an alignment film on the substrate patterning with the spacer and the contact hole filing layer.

Abstract translation: 本发明的实施例公开了薄膜晶体管阵列基板，其制造方法和显示装置。 一种制造薄膜晶体管阵列基板的方法，包括：在形成有薄膜晶体管阵列的基板上形成树脂层，通过使用掩模工艺对树脂层进行图案化以形成间隔物和接触孔填充层， 孔填充层用于填充薄膜晶体管阵列基板上的接触孔; 在衬底上用间隔物和接触孔填充层图案化形成取向膜。