ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF, LIQUID CRYSTAL CELL AND DISPLAY APPARATUS

    公开(公告)号:US20250093722A1

    公开(公告)日:2025-03-20

    申请号:US18578363

    申请日:2022-07-26

    Abstract: An array substrate, a method for manufacturing an array substrate, a liquid crystal cell and a display apparatus are provided. The array substrate includes: a first base substrate; thin film transistors; a first planarization layer; a common electrode on a side of the first planarization layer away from the thin film transistors; a first dielectric layer on a side of the common electrode away from the first planarization layer; first pixel electrodes on a side of the first dielectric layer away from the common electrode; the first pixel electrodes are electrically connected to the thin film transistors in a one-to-one correspondence through first vias extending through the first dielectric layer and the first planarization layer; a surface of each first pixel electrode away from the first base substrate is provided with a first groove at least corresponding to a corresponding first via.

    PIXEL CIRCUIT AND DRIVING METHOD THEREFOR, DISPLAY SUBSTRATE, AND DISPLAY APPARATUS

    公开(公告)号:US20240395197A1

    公开(公告)日:2024-11-28

    申请号:US17772029

    申请日:2021-06-30

    Abstract: A pixel circuit includes a first driving circuit, a first control circuit, a second driving circuit and a second control circuit. The first driving circuit is configured to write a first data signal into a first node in response to a scanning signal. The first control circuit is configured to transmit a first voltage signal to the first driving circuit, and transmit a first driving signal generated by the first driving circuit according to a voltage of the first node and the first voltage signal in response to an enable signal. The second driving circuit is configured to write a second data signal into a second node in response to the scanning signal. The second control circuit is configured to transmit a second driving signal generated by the second driving circuit according to a voltage of the second node and the first voltage signal in response to a control signal.

    Transparent Display Panel and Display Apparatus

    公开(公告)号:US20240258327A1

    公开(公告)日:2024-08-01

    申请号:US18020258

    申请日:2022-06-29

    CPC classification number: H01L27/124 H01L25/167

    Abstract: A transparent display panel includes: a substrate (100), and multiple repeating units (10) arranged in an array on the substrate. The non-transmissive region (A1) of the repeating unit includes: at least one pixel unit (P), N sets of first traces (11) extending in a first direction (X) and M sets of second traces (12) extending in a second direction (Y) electrically connected to the pixel unit. A set of first traces includes: multiple first signal lines (111) and at least one second signal line (112), an orthographic projection of at least one second signal line on substrate covers that of at least two first signal lines on substrate; or, a set of second traces includes: multiple third signal lines (121) and at least one fourth signal line (122), orthographic projection of at least one fourth signal line on substrate covers that of at least two third signal lines on substrate.

    SHIFT REGISTER, DRIVING METHOD, DRIVING CONTROL CIRCUIT, AND DISPLAY DEVICE

    公开(公告)号:US20220383822A1

    公开(公告)日:2022-12-01

    申请号:US17628779

    申请日:2021-04-09

    Abstract: A shift register, a driving method, a driving control circuit and a display device. The method comprises: at a data refresh stage (T10), applying to an input signal end (IP) an input signal having a pulse level, applying a control clock pulse signal to a control clock signal end, and applying a noise reduction clock pulse signal to a noise reduction clock signal end; at a noise reduction holding phase (T21-1), applying a fixed voltage signal to the input signal end (IP), applying a fixed voltage signal to the control clock signal end, and applying a fixed voltage signal to the noise reduction clock signal end; and at a noise reduction enhancement stage (T22-1), applying a fixed voltage signal to the input signal end (IP), applying a fixed voltage signal to the control clock signal end, and applying a clock pulse signal to the noise reduction clock signal end.

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