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71.
公开(公告)号:US20250093722A1
公开(公告)日:2025-03-20
申请号:US18578363
申请日:2022-07-26
Applicant: BOE Technology Group Co., Ltd.
Inventor: Yunping DI , Chenyang ZHANG , Lizhong WANG , Yichi ZHANG , Haoliang ZHENG , Zhen ZHANG
IPC: G02F1/1368 , G02F1/1362 , H10D86/40 , H10D86/60
Abstract: An array substrate, a method for manufacturing an array substrate, a liquid crystal cell and a display apparatus are provided. The array substrate includes: a first base substrate; thin film transistors; a first planarization layer; a common electrode on a side of the first planarization layer away from the thin film transistors; a first dielectric layer on a side of the common electrode away from the first planarization layer; first pixel electrodes on a side of the first dielectric layer away from the common electrode; the first pixel electrodes are electrically connected to the thin film transistors in a one-to-one correspondence through first vias extending through the first dielectric layer and the first planarization layer; a surface of each first pixel electrode away from the first base substrate is provided with a first groove at least corresponding to a corresponding first via.
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公开(公告)号:US20240395197A1
公开(公告)日:2024-11-28
申请号:US17772029
申请日:2021-06-30
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: Seungwoo HAN , Haoliang ZHENG , Li XIAO , Dongni LIU , Liang CHEN , Hao CHEN , Jiao ZHAO , Minghua XUAN
IPC: G09G3/3233 , G09G3/20
Abstract: A pixel circuit includes a first driving circuit, a first control circuit, a second driving circuit and a second control circuit. The first driving circuit is configured to write a first data signal into a first node in response to a scanning signal. The first control circuit is configured to transmit a first voltage signal to the first driving circuit, and transmit a first driving signal generated by the first driving circuit according to a voltage of the first node and the first voltage signal in response to an enable signal. The second driving circuit is configured to write a second data signal into a second node in response to the scanning signal. The second control circuit is configured to transmit a second driving signal generated by the second driving circuit according to a voltage of the second node and the first voltage signal in response to a control signal.
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公开(公告)号:US20240321186A1
公开(公告)日:2024-09-26
申请号:US18680595
申请日:2024-05-31
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: Jiao ZHAO , Li XIAO , Minghua XUAN , Haoliang ZHENG , Dongni LIU , Jing LIU , Qi QI , Zhenyu ZHANG , Liang CHEN , Hao CHEN , Lijun YUAN
CPC classification number: G09G3/32 , G11C19/28 , H01L25/0753 , H01L27/0296 , H01L27/124 , H01L33/62 , G09G2300/026 , G09G2310/0286 , G09G2330/04
Abstract: An array substrate has a display area and includes at least one pixel group, at least one pixel circuit group and at least one shift register circuit. The at least one pixel group is disposed in the display area. Each pixel group includes a plurality of pixels arranged in an array. Each pixel circuit group is disposed between two adjacent rows of pixels or two adjacent columns of pixels in a corresponding pixel group. Each pixel circuit group includes at least one pixel driving sub-circuit group. A shift register circuit is disposed between two rows of pixels or two columns of pixels that are different from two rows of pixels or two columns of pixels between which a pixel driving sub-circuit group is disposed.
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公开(公告)号:US20240258327A1
公开(公告)日:2024-08-01
申请号:US18020258
申请日:2022-06-29
Applicant: BOE Technology Group Co., Ltd.
Inventor: Dongni LIU , Minghua XUAN , Zhenyu ZHANG , Haoliang ZHENG , Shunhang ZHANG , Wanzhi CHEN , Qi QI , Jing LIU
CPC classification number: H01L27/124 , H01L25/167
Abstract: A transparent display panel includes: a substrate (100), and multiple repeating units (10) arranged in an array on the substrate. The non-transmissive region (A1) of the repeating unit includes: at least one pixel unit (P), N sets of first traces (11) extending in a first direction (X) and M sets of second traces (12) extending in a second direction (Y) electrically connected to the pixel unit. A set of first traces includes: multiple first signal lines (111) and at least one second signal line (112), an orthographic projection of at least one second signal line on substrate covers that of at least two first signal lines on substrate; or, a set of second traces includes: multiple third signal lines (121) and at least one fourth signal line (122), orthographic projection of at least one fourth signal line on substrate covers that of at least two third signal lines on substrate.
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75.
公开(公告)号:US20240185772A1
公开(公告)日:2024-06-06
申请号:US18533211
申请日:2023-12-08
Applicant: BOE Technology Group Co., Ltd.
Inventor: Li XIAO , Haoliang ZHENG , Minghua XUAN , Seungwoo HAN , Hao CHEN , Dongni LIU , Jiao ZHAO , Liang CHEN , Qi QI
CPC classification number: G09G3/32 , G09G3/2007 , G09G3/3208
Abstract: A drive method for a display panel, wherein the display panel includes a plurality of current data lines, a plurality of time-length data lines, a first current selection signal line, a second current selection signal line, a first time-length selection signal line and a second time-length selection signal line, at least one current data line is connected with the first current selection signal line or the second current selection signal line, and at least one time-length data line is connected with the first time-length selection signal line or the second time-length selection signal line; the method includes: providing a valid level signal to the first time-length selection signal line, the second time-length selection signal line, the first current selection signal line and the second current selection signal line.
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76.
公开(公告)号:US20230351968A1
公开(公告)日:2023-11-02
申请号:US18338577
申请日:2023-06-21
Applicant: BOE Technology Group Co., Ltd.
Inventor: Zhenyu ZHANG , Li XIAO , Dongni LIU , Liang CHEN , Hao CHEN , Haoliang ZHENG , Minghua XUAN , Jiao ZHAO
IPC: G09G3/3258
CPC classification number: G09G3/3258 , G09G2300/0439 , G09G2310/061 , G09G2320/0233 , G09G2360/14 , G06F3/0421
Abstract: Provided are a photoelectric detection circuit and a driving method thereof, a display apparatus and a manufacturing method thereof. The photoelectric detection circuit includes: a first reset sub-circuit, a second reset sub-circuit, a first storage sub-circuit, a data read sub-circuit and a photosensitive device. A first terminal of the data read sub-circuit, a first terminal of the first storage sub-circuit, a first electrode of the photosensitive device and a first terminal of the first reset sub-circuit are connected to a first node. A second electrode of the photosensitive device is connected to a common voltage line. The data read sub-circuit is configured to transmit a voltage of the first node to a data read line in response to a signal of a scan line. The first reset sub-circuit is configured to reset the voltage of the first node.
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公开(公告)号:US20230351943A1
公开(公告)日:2023-11-02
申请号:US17636897
申请日:2021-04-21
Applicant: BOE Technology Group Co., Ltd.
Inventor: Li XIAO , Haoliang ZHENG , Minghua XUAN , Seungwoo HAN , Hao CHEN , Dongni LIU , Jiao ZHAO , Liang CHEN , Qi QI
CPC classification number: G09G3/32 , G09G3/2007 , G09G2300/0861 , G09G2300/0852 , G09G2300/0819 , G09G2320/0247 , G09G2320/0233 , G09G2310/08
Abstract: Disclosed are a pixel circuit and a drive method for the same, and a display panel and a drive method for the same. The pixel circuit is configured to drive a light-emitting element to emit light, including: a current control sub-circuit and a time-length control sub-circuit. The current control sub-circuit is electrically connected to a current data terminal, a scanning signal terminal, a reset signal terminal, an initial signal terminal, a light-emitting signal terminal, a first power terminal, a first node, and a second node, respectively. The time-length control sub-circuit is electrically connected to a first control terminal, a second control terminal, a time-length data terminal, a ground terminal, a light-emitting signal terminal, a high-frequency input terminal, and the first node, respectively.
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公开(公告)号:US20230260453A1
公开(公告)日:2023-08-17
申请号:US18307416
申请日:2023-04-26
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: Jiao ZHAO , Li XIAO , Minghua XUAN , Haoliang ZHENG , Dongni LIU , Jing LIU , Qi QI , Zhenyu ZHANG , Liang CHEN , Hao CHEN , Lijun YUAN
CPC classification number: G09G3/32 , G11C19/28 , H01L25/0753 , H01L27/0296 , H01L27/124 , H01L33/62 , G09G2300/026 , G09G2310/0286 , G09G2330/04
Abstract: An array substrate includes M pixel lines and N pixel circuit groups. The M pixel lines are disposed in a display area and arranged in a first direction. The N pixel circuit groups are arranged in the first direction. M is an integer greater than or equal to 2, and N is a positive integer less than M. A pixel circuit group of the N pixel circuit groups is electrically connected to adjacent two pixel lines of the M pixel lines, and the first direction is one of a row direction and a column direction.
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公开(公告)号:US20230071948A1
公开(公告)日:2023-03-09
申请号:US17984469
申请日:2022-11-10
Applicant: BOE Technology Group Co., Ltd.
Inventor: Liang CHEN , Minghua XUAN , Dongni LIU , Haoliang ZHENG , Li XIAO , Zhenyu ZHANG , Hao CHEN , Ke WANG
IPC: G02F1/1362 , H01L27/32
Abstract: The present disclosure discloses a display panel and a display device. The display panel includes: a base substrate, including a plurality of substrate via holes located in a display area of the display panel; and a plurality of driving signal lines and a plurality of bonding terminals, respectively located on different sides of the base substrate. At least one of the plurality of driving signal lines is electrically connected to at least one of the plurality of bonding terminals through the substrate via hole(s).
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公开(公告)号:US20220383822A1
公开(公告)日:2022-12-01
申请号:US17628779
申请日:2021-04-09
Applicant: BOE Technology Group Co., Ltd.
Inventor: Guangliang SHANG , Jie ZHANG , Shuo HUANG , Libin LIU , Shiming SHI , Hao LIU , Haoliang ZHENG , Xing YAO
IPC: G09G3/3266 , G11C19/28 , G09G3/36
Abstract: A shift register, a driving method, a driving control circuit and a display device. The method comprises: at a data refresh stage (T10), applying to an input signal end (IP) an input signal having a pulse level, applying a control clock pulse signal to a control clock signal end, and applying a noise reduction clock pulse signal to a noise reduction clock signal end; at a noise reduction holding phase (T21-1), applying a fixed voltage signal to the input signal end (IP), applying a fixed voltage signal to the control clock signal end, and applying a fixed voltage signal to the noise reduction clock signal end; and at a noise reduction enhancement stage (T22-1), applying a fixed voltage signal to the input signal end (IP), applying a fixed voltage signal to the control clock signal end, and applying a clock pulse signal to the noise reduction clock signal end.
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