公开(公告)号：US20180323215A1

公开(公告)日：2018-11-08

申请号：US15587087

申请日：2017-05-04

申请人： ARM Limited

发明人： Yew Keong Chong ,  Sriram Thyagarajan ,  Vincent Philippe Schuppe

IPC分类号： H01L27/118 ,  H01L27/02

CPC分类号： H01L27/11807 ,  G06F17/5068 ,  H01L27/0207 ,  H01L2027/11866 ,  H01L2027/11881

摘要： Various implementations described herein are directed to an integrated circuit having multiple access wires including a first access wire coupled to a first access port of the integrated circuit and a second access wire coupled to a second access port of the integrated circuit. The integrated circuit may include inverter circuitry having a first plurality of inverters coupled to the first access wire and a second plurality of inverters coupled to the second access wire. The first plurality of inverters may be positioned adjacent to the second plurality of inverters in an alternating manner.

公开(公告)号：US20180225402A9

公开(公告)日：2018-08-09

申请号：US14528314

申请日：2014-10-30

申请人： ARM Limited

发明人： Paul DE DOOD ,  Marlin Wayne Frederick, JR. ,  Jerry Chaoyuan Wang ,  Brian Douglas Ngai Lee ,  Brian Tracy Cline ,  Xiaoqing Xu ,  Andy Wangkun Chen ,  Yew Keong Chong ,  Tom Shore ,  Sriram Thyagarajan ,  Gus Yeung ,  Yanbin Jiang ,  Emmanuel Jean Marie Olivier Pacaud ,  Matthieu Domonique Henri Pauly ,  Sylvia Xiuhui Li ,  Thanusree Achuthan ,  Daniel J. Albers ,  David William Granda

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081

摘要： A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimised during generation of the layout of the cell.

公开(公告)号：US10020031B2

公开(公告)日：2018-07-10

申请号：US15401588

申请日：2017-01-09

申请人： ARM Limited

发明人： Yew Keong Chong ,  Andy Wangkun Chen ,  Sriram Thyagarajan ,  Gus Yeung ,  James Dennis Dodrill

IPC分类号： G11C8/18 ,  G11C7/10 ,  G11C29/50 ,  G11C5/14 ,  G11C8/06 ,  G11C29/02 ,  G11C29/00

CPC分类号： G11C7/1012 ,  G11C5/141 ,  G11C8/06 ,  G11C8/18 ,  G11C29/022 ,  G11C29/023 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50012 ,  G11C29/702

摘要： Various implementations described herein are directed to a method of integrated circuit design and fabrication. In the implementation of a memory integrated circuit, the floorplan of the integrated circuit comprises memory blocks, where instantiations of the memory blocks are optimized to satisfy timing specifications while minimizing power consumption or not significantly contributing to leakage current.

公开(公告)号：US20180173822A1

公开(公告)日：2018-06-21

申请号：US15387373

申请日：2016-12-21

申请人： ARM Limited

发明人： Hongwei Zhu ,  Mouli Rajaram Chollangi ,  Hemant Joshi ,  Yew Keong Chong ,  Satinderjit Singh ,  Betsie Jacob ,  Neeraj Dogra ,  Sriram Thyagarajan

IPC分类号： G06F17/50 ,  G06F17/30

CPC分类号： G06F17/5009 ,  G06F17/30289 ,  G06F17/5068 ,  G06F2217/12

摘要： Various implementations described herein are directed to a computing device. The computing device may include a mapper module that receives a user configuration input of a destination corner for building a destination corner database. The mapper module may include a decision making engine that decides fabrication parameters for building the destination corner database based on the verified user configuration input and memory compiler metadata. The computing device may include a builder module that performs a simulation of the destination corner based on the fabrication parameters, collects simulation results data associated with the simulation, and builds the destination corner database for the destination corner based on the simulation results data and source corner data. The computing device may include a memory compiler that accesses the destination corner database and generates memory instance structures and their electronic digital automation (EDA) views for the destination corner based on the destination corner database.

公开(公告)号：US09111596B2

公开(公告)日：2015-08-18

申请号：US13967908

申请日：2013-08-15

申请人： ARM Limited

发明人： Sriram Thyagarajan ,  Yew Keong Chong ,  Wang-Kun Chen ,  Gus Yeung

IPC分类号： G11C7/10 ,  G11C8/08 ,  G11C8/06

CPC分类号： G11C8/08 ,  G11C7/10 ,  G11C8/06

摘要： A memory device comprises an array of bitcells arranged as a plurality of rows of bitcells and a plurality of columns of bitcells, and has a plurality of wordlines and a plurality of readout channels. A control unit is configured to control access to the array of bitcells, wherein in response to a memory access request specifying a memory address the control unit is configured to activate a selected wordline and to activate the plurality of readout channels, and to access a row of bitcells in said array storing a data word and addressed by the memory address. The data word consists of a number of data bits given by a number of bitcells in each row of bitcells. The control unit is further configured to be responsive to a masking signal and, when the masking signal is asserted when said memory access request is received, the control unit is configured to activate only a portion of the selected wordline and a portion of the plurality of readout channels, such that only a portion of the data word is accessed.

摘要翻译： 存储器件包括排列成多行比特单元和多列比特单元的位单元阵列，并且具有多个字线和多个读出通道。 控制单元被配置为控制对位单元阵列的访问，其中响应于指定存储器地址的存储器访问请求，控制单元被配置为激活所选择的字线并激活多个读出通道，并且访问行 所述阵列中的位单元存储数据字并由存储器地址寻址。 数据字由每行位单元中的多个位单元给出的多个数据位组成。 所述控制单元还被配置为响应于屏蔽信号，并且当接收到所述存储器访问请求时屏蔽信号被断言时，所述控制单元被配置为仅激活所选字线的一部分和所述多个 读出通道，使得仅访问数据字的一部分。