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公开(公告)号：US20160253179A1
公开(公告)日：2016-09-01
申请号：US15154381
申请日：2016-05-13
Applicant: Apple Inc.
Inventor： Jeffry E. Gonion
CPC classification number: G06F9/3836 , G06F8/445 , G06F9/30021 , G06F9/30036 , G06F9/30043 , G06F9/30072 , G06F9/30192 , G06F9/3822 , G06F9/3853
Abstract: A processor may include a vector functional unit that supports concurrent operations on multiple data elements of a maximum element size. The functional unit may also support concurrent execution of multiple distinct vector program instructions, where the multiple vector instructions each operate on multiple data elements of less than the maximum element size.
Abstract translation: 处理器可以包括支持对最大元素大小的多个数据元素的并行操作的向量功能单元。 功能单元还可以支持并行执行多个不同向量程序指令，其中多个向量指令各自对小于最大元素大小的多个数据元素进行操作。
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公开(公告)号：US09390058B2
公开(公告)日：2016-07-12
申请号：US14034680
申请日：2013-09-24
Applicant: Apple Inc.
Inventor： Jeffry E. Gonion
CPC classification number: G06F15/78 , G06F9/30036 , G06F9/30105 , G06F9/3013
Abstract: In an embodiment, a processor may be configured to dynamically infer one or more attributes of input and/or output registers of an instruction, given the attributes corresponding to at least one input registers. The inference may be made at the issue circuit/stage of the processor, for those registers that do not have attribute information at the issue circuit/stage. In an embodiment, the processor may also include a register attribute tracker configured to track attributes of registers prior to the issue stage of the processor pipeline. The processor may feed back, to the register attribute tracker, inferred attributes and the register addresses of the registers to which the inferred attributes apply. The register attribute tracker may be configured to may associate the inferred attribute with the identified register attribute tracker may also be configured to infer input register attributes from other input register attributes.
Abstract translation: 在一个实施例中，给定与至少一个输入寄存器对应的属性，处理器可以被配置为动态地推断指令的输入和/或输出寄存器的一个或多个属性。 推理可以在处理器的发布电路/阶段进行，对于那些在发布电路/阶段没有属性信息的寄存器。 在一个实施例中，处理器还可以包括配置为在处理器流水线的发布阶段之前跟踪寄存器的属性的寄存器属性跟踪器。 处理器可以向注册属性跟踪器反馈推断的属性和推断的属性适用的寄存器的寄存器地址。 寄存器属性跟踪器可以被配置为可以将推断的属性与所识别的寄存器属性跟踪器相关联，还可以被配置为从其他输入寄存器属性推断输入寄存器属性。
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73.发明授权公开(公告)号：US09342304B2
公开(公告)日：2016-05-17
申请号：US13628826
申请日：2012-09-27
Applicant: Apple Inc.
Inventor： Jeffry E. Gonion
CPC classification number: G06F9/30036 , G06F8/4441 , G06F9/30014 , G06F9/30072
Abstract: Embodiments of a system and a method in which a processor may execute instructions that cause the processor to receive an input vector and a control vector are disclosed. The executed instructions may also cause the processor to perform a fixed-value addition operation dependent upon the input vector and the control vector.
Abstract translation: 公开了一种系统和方法的实施例，其中处理器可以执行使处理器接收输入向量和控制向量的指令。 执行的指令还可以使处理器执行取决于输入向量和控制向量的固定值加法运算。
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74.发明授权Processing vectors using a wrapping rotate previous instruction in the macroscalar architecture 有权使用包装的处理向量在宏级结构中旋转先前的指令公开(公告)号：US09335997B2
公开(公告)日：2016-05-10
申请号：US13630596
申请日：2012-09-28
Applicant: Apple Inc.
Inventor： Jeffry E. Gonion
CPC classification number: G06F9/30036 , G06F8/441 , G06F8/4441 , G06F9/30032 , G06F9/30072
Abstract: Embodiments of a system and a method in which a processor may execute instructions that cause the processor to receive an operand vector, a selection vector, and a control vector are disclosed. The executed instructions may also cause the processor to perform a wrapping rotate previous operation dependent upon the input vectors.
Abstract translation: 公开了一种系统和方法的实施例，其中处理器可以执行使处理器接收操作数向量，选择向量和控制向量的指令。 执行的指令还可以使得处理器执行包装，以取决于输入向量旋转先前的操作。
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公开(公告)号：US09317284B2
公开(公告)日：2016-04-19
申请号：US14034658
申请日：2013-09-24
Applicant: Apple Inc.
Inventor： Jeffry E. Gonion , Alexander C. Klaiber
IPC: G06F9/30
CPC classification number: G06F9/30036 , G06F9/30021 , G06F9/3004 , G06F9/3838
Abstract: In an embodiment, a processor may implement a vector hazard check instruction to detect dependencies between vector memory operations based on the addresses of the vectors accessed by the vector memory operations. The addresses may be specified via a base address and a vector of indexes for each vector. In an embodiment, one of the base addresses may be an implied (or assumed) zero address, reducing the number of operands of the hazard check instruction.
Abstract translation: 在一个实施例中，处理器可以实施向量危险检查指令，以基于由向量存储器操作所访问的向量的地址来检测向量存储器操作之间的依赖性。 可以通过基地址和每个向量的索引向量来指定地址。 在一个实施例中，基地址之一可以是隐含（或假设的）零地址，减少了危险检查指令的操作数。
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Patent Agency Ranking
公开(公告)号：US20150178087A1
公开(公告)日：2015-06-25
申请号：US14137232
申请日：2013-12-20
Applicant: Apple Inc.
Inventor： Jeffry E. Gonion
CPC classification number: G06F9/3838 , G06F9/30018 , G06F9/30036 , G06F9/30076
Abstract: A hazard check instruction has operands that specify addresses of vector elements to be read by first and second vector memory operations. The hazard check instruction outputs a dependency vector identifying, for each element position of the first vector corresponding to the first vector memory operation, which element position of the second vector that the element of the first vector depends on (if any). In an embodiment, the addresses of the vector memory operations are specified using a base address for each vector memory operation and a vector that is shared by both vector memory operations. In an embodiment, the operands may include predicates for one or both of the vector memory operations, indicating which vector elements are active. The dependency vector may be qualified by the predicates, indicating dependencies only for active elements.
Abstract translation: 危险检查指令具有指定要通过第一和第二向量存储器操作读取的向量元素的地址的操作数。 危险检查指令输出依赖性向量，对于与第一向量存储器操作相对应的第一向量的每个元素位置，识别第一向量的元素所依赖的第二向量的哪个元素位置（如果有的话）。 在一个实施例中，使用每个向量存储器操作的基址和由向量存储器操作共享的向量来指定向量存储器操作的地址。 在一个实施例中，操作数可以包括向量存储器操作中的一个或两个的谓词，指示哪些向量元素是活动的。 依赖向量可以由谓词限定，仅指示活动元素的依赖性。
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公开(公告)号：US20150089187A1
公开(公告)日：2015-03-26
申请号：US14034651
申请日：2013-09-24
Applicant: APPLE INC.
Inventor： Jeffry E. Gonion
CPC classification number: G06F9/30036 , G06F9/30018 , G06F9/30021 , G06F9/30072 , G06F9/3013 , G06F9/3838 , G06F15/8061
Abstract: A hazard check instruction has operands that specify addresses of vector elements to be read by first and second vector memory operations. The hazard check instruction outputs a dependency vector identifying, for each element position of the first vector corresponding to the first vector memory operation, which element position of the second vector that the element of the first vector depends on (if any). In an embodiment, at least one of the vector memory operations has addresses specified using a scalar address in the operands (and a vector attribute associated with the vector). In an embodiment, the operands may include predicates for one or both of the vector memory operations, indicating which vector elements are active. The dependency vector may be qualified by the predicates, indicating dependencies only for active elements.
Abstract translation: 危险检查指令具有指定要通过第一和第二向量存储器操作读取的向量元素的地址的操作数。 危险检查指令输出依赖性向量，对于与第一向量存储器操作相对应的第一向量的每个元素位置，识别第一向量的元素所依赖的第二向量的哪个元素位置（如果有的话）。 在一个实施例中，向量存储器操作中的至少一个具有使用操作数中的标量地址指定的地址（以及与向量相关联的向量属性）。 在一个实施例中，操作数可以包括向量存储器操作中的一个或两个的谓词，指示哪些向量元素是活动的。 依赖向量可以由谓词限定，仅指示活动元素的依赖性。
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公开(公告)号：US20140331020A1
公开(公告)日：2014-11-06
申请号：US14330320
申请日：2014-07-14
Applicant: APPLE INC.
Inventor： Ian C. Hendry , Rajabali Koduri , Jeffry E. Gonion
CPC classification number: G06F3/0647 , G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F3/0604 , G06F3/0625 , G06F3/065 , G06F3/0673 , G06F12/0292 , G06F12/06 , G06F12/0646 , G06F12/08 , G06F17/30147 , G06F2003/0697 , Y02D10/14 , Y02D50/20
Abstract: Systems, methods, and devices for dynamically mapping and remapping memory when a portion of memory is activated or deactivated are provided. In accordance with an embodiment, an electronic device may include several memory banks, one or more processors, and a memory controller. The memory banks may store data in hardware memory locations and may be independently deactivated. The processors may request the data using physical memory addresses, and the memory controller may translate the physical addresses to hardware memory locations. The memory controller may use a first memory mapping function when a first number of memory banks is active and a second memory mapping function when a second number is active. When one of the memory banks is to be deactivated, the memory controller may copy data from only the memory bank that is to be deactivated to the active remainder of memory banks.
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79.发明申请PROCESSING VECTORS USING WRAPPING MINIMA AND MAXIMA INSTRUCTIONS IN THE MACROSCALAR ARCHITECTURE 有权使用包装MINIMA和MAXIMA指令在宏观架构中处理向量公开(公告)号：US20130036293A1
公开(公告)日：2013-02-07
申请号：US13625164
申请日：2012-09-24
Applicant: Apple Inc.
Inventor： Jeffry E. Gonion
IPC: G06F15/76
CPC classification number: G06F9/30014 , G06F8/4441 , G06F9/30018 , G06F9/30036 , G06F9/30072 , G06F9/3838 , G06F9/3842
Abstract: Embodiments of a system and a method in which a processor may execute instructions that cause the processor to receive an input vector and a control vector are disclosed. The executed instructions may also cause the processor to perform a minima or maxima operation on another input vector dependent upon the input vector and the control vector.
Abstract translation: 公开了一种系统和方法的实施例，其中处理器可以执行使处理器接收输入向量和控制向量的指令。 执行的指令还可以使得处理器根据输入向量和控制向量对另一个输入向量执行最小或最大值操作。
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80.发明申请公开(公告)号：US20130024655A1
公开(公告)日：2013-01-24
申请号：US13628826
申请日：2012-09-27
Applicant: APPLE INC.
Inventor： Jeffry E. Gonion
IPC: G06F15/78
CPC classification number: G06F9/30036 , G06F8/4441 , G06F9/30014 , G06F9/30072
Abstract: Embodiments of a system and a method in which a processor may execute instructions that cause the processor to receive an input vector and a control vector are disclosed. The executed instructions may also cause the processor to perform a fixed-value addition operation dependent upon the input vector and the control vector.
Abstract translation: 公开了一种系统和方法的实施例，其中处理器可以执行使处理器接收输入向量和控制向量的指令。 执行的指令还可以使处理器执行取决于输入向量和控制向量的固定值加法运算。
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