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    Displays with multiple scanning modes
    71.
    发明授权
    Displays with multiple scanning modes 有权

    公开(公告)号：US10109240B2

    公开(公告)日：2018-10-23

    申请号：US15403070

    申请日：2017-01-10

    Applicant: Apple Inc.

    Inventor： Shih Chang Chang ,  Keitaro Yamashita ,  Shin-Hung Yeh ,  Ting-Kuo Chang ,  Abbas Jamshidi Roudbari ,  Chin-Wei Lin

    IPC: G09G3/3266 ,  G09G3/3291 ,  G09G5/18 ,  G06T19/00 ,  G09G3/36

    Abstract: An electronic device may include a display such as a light-emitting diode display. The electronic device may be a head-mounted device that provides a virtual reality or augmented reality environment to a user. To reduce artifacts in the display, a display may be operable in both a normal scanning mode and a partial scanning mode. In the normal scanning mode, every row of the display may be scanned in each frame. In the partial scanning mode, only a subset of the rows of the display may be scanned in each frame. The display may have a higher refresh rate in the partial scanning mode than in the normal scanning mode. The gate driver circuitry may include a shift register that includes a plurality of register circuits. At least one register circuit may have a first input and a second input that is different than the first input.

    Display with shallow contact holes and reduced metal residue at planarization layer steps
    72.
    发明授权
    Display with shallow contact holes and reduced metal residue at planarization layer steps 有权

    公开(公告)号：US10101853B2

    公开(公告)日：2018-10-16

    申请号：US15260137

    申请日：2016-09-08

    Applicant: Apple Inc.

    Inventor： Yu Cheng Chen ,  Keitaro Yamashita ,  Abbas Jamshidi Roudbari ,  Hirokazu Yamagata ,  Ting-Kuo Chang

    IPC: H01L27/12 ,  G06F3/041 ,  G06F3/044

    Abstract: Thin-film transistor circuitry for a display may include conductive layers such as transparent conductive layers and metal layers and may include dielectric layers. The dielectric layers may include buffer layers, interlayer dielectric, gate insulator, and organic planarization layers. The organic planarization layers may be patterned photolithographically to form vias, trenches, and other structures. Trenches may be formed by removing the planarization layer in a strip. When planarization material is removed for forming a trench or other structure, a step is formed in the planarization material. Metal lines such as data lines and other signal lines may cross steps in the planarization material. To prevent shorts between lines, a step may have protrusions that help eliminate metal etch residue. Vias may be reduced in depth by forming metal bumps and dielectric bumps under the vias and by forming other via structures.

    Displays with Gate Driver Circuitry for Discharging Display Pixels
    79.
    发明申请
    Displays with Gate Driver Circuitry for Discharging Display Pixels 审中-公开
    显示器具有用于放电显示像素的栅极驱动器电路

    公开(公告)号：US20170031477A1

    公开(公告)日：2017-02-02

    申请号：US14988586

    申请日：2016-01-05

    Applicant: Apple Inc.

    Inventor： Abbas Jamshidi Roudbari ,  Keitaro Yamashita

    IPC: G06F3/044

    CPC classification number: G06F3/044 ,  G06F3/0418

    Abstract: A touch screen display may include gate line driver circuitry coupled to a display pixel array. The gate driver circuitry may include gate drivers connected in a chain. A given one of the gate drivers may include a set-reset latch. The set-reset latch may have a set input and a reset input. A logic gating circuit such as a logic NOR gate may have an output directly connected to the set input. The NOR gate may have a first input coupled to an output of a preceding gate driver in the chain and a second input coupled to an output of a succeeding gate driver. The reset input may be coupled to the output of the preceding gate driver. Gate line output signals may be simultaneously asserted for each of the drivers without generating unstable scenarios where logic high signals are provided to the set and reset inputs.

    Abstract translation: 触摸屏显示器可以包括耦合到显示像素阵列的栅极线驱动器电路。 栅极驱动器电路可以包括连接在链中的栅极驱动器。 给定的一个栅极驱动器可以包括设置复位锁存器。 设置复位锁存器可以具有置位输入和复位输入。 诸如逻辑或非门的逻辑选通电路可以具有直接连接到设定输入的输出。 NOR门可以具有耦合到链中的先前栅极驱动器的输出的第一输入和耦合到后续栅极驱动器的输出的第二输入。 复位输入可以耦合到先前的栅极驱动器的输出端。 可以为每个驱动器同时断言栅极线输出信号，而不会产生将逻辑高电平信号提供给置位和复位输入的不稳定情况。

    Thin film transistor with increased doping regions
    80.
    发明授权
    Thin film transistor with increased doping regions 失效
    掺杂区域增加的薄膜晶体管

    公开(公告)号：US08704232B2

    公开(公告)日：2014-04-22

    申请号：US13629531

    申请日：2012-09-27

    Applicant: Apple Inc.

    Inventor： Abbas Jamshidi Roudbari ,  Cheng-Ho Yu ,  Shih Chang Chang ,  Ting-Kuo Chang

    IPC: H01L29/10

    CPC classification number: H01L29/78675 ,  H01L27/1222 ,  H01L29/78624 ,  H01L29/78645 ,  H01L29/78696

    Abstract: A transistor that may be used in electronic displays to selectively activate one or more pixels. The transistor includes a metal layer, a silicon layer deposited on at least a portion of the metal layer, the silicon layer includes an extension portion that extends a distance past the metal layer, and at least three lightly doped regions positioned in the silicon layer. The at least three lightly doped regions have a lower concentration of doping atoms than other portions of the silicon layer forming the transistor.

    Abstract translation: 可用于电子显示器中以选择性地激活一个或多个像素的晶体管。 晶体管包括金属层，沉积在金属层的至少一部分上的硅层，硅层包括延伸距离金属层的延伸部分和位于硅层中的至少三个轻掺杂区域。 所述至少三个轻掺杂区域具有比形成晶体管的硅层的其它部分更低的掺杂原子浓度。

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