公开(公告)号：US10545867B2

公开(公告)日：2020-01-28

申请号：US15739243

申请日：2016-05-10

Applicant: Sanechips Technology Co., Ltd.

Inventor： Chuang Bao ,  Zhenlin Yan ,  Chunhui Zhang ,  Kang An

IPC: G06F12/00 ,  G06F12/0802 ,  G06F12/0879 ,  H04L29/06 ,  H04L29/08

Abstract: A device, method, and a data storage medium, configured to enhance an item access bandwidth and atomic operation are provided. The device comprises: a comparison module, a cache, and a distribution module; wherein the comparison module is configured to receive a query request from a service side, determine whether an address pointed to by the query request and an item address stored in the cache are identical. If so, and a valid identifier vld is valid, the comparison module is configured to directly return the item data stored in the cache to the service side without initiating a request for looking up an off-chip memory, so as to reduce a frequency of accessing the off-chip memory. If not, the comparison module is configured to initiate a request for looking up the off-chip memory, so as to process, according to a first preconfigured rule, item data returned by the off-chip memory.

公开(公告)号：US10481957B2

公开(公告)日：2019-11-19

申请号：US15763996

申请日：2016-07-01

Applicant: SANECHIPS TECHNOLOGY CO., LTD.

Inventor： Bo Wen ,  Qingxin Cao

IPC: G06F9/52 ,  G06F9/30 ,  G06F9/48 ,  G06F9/38

Abstract: A processor and a task processing method therefor, and a storage medium. The method comprises: a scalar calculation module executing parameter calculation of a current task, and storing a parameter obtained through calculation in a PBUF; when the parameter calculation of the current task is completed, executing a first instruction or second instruction for inter-core synchronization, and storing the first instruction or the second instruction in the PBUF (301); a vector calculation module reading the parameter from the PBUF, storing the read parameter in a shadow register; when the first instruction or the second instruction is read from the PBUF, storing all the modified parameters in the shadow register in a work register within a period (302); and the vector calculation module executing vector calculation of the current task according to the parameter in the work register (303).

公开(公告)号：US10411803B2

公开(公告)日：2019-09-10

申请号：US15564924

申请日：2015-11-11

Applicant: Sanechips Technology Co., Ltd.

Inventor： Huajie Fu ,  Yantao Gu

IPC: H04J14/02 ,  H04B10/2507 ,  G02B6/28 ,  G02F1/35

Abstract: Disclosed are a strong filter compensation method and device, and a computer storage medium. The method includes filtering out a high-frequency noise by delay summation; determining a correct path from one or more interference item paths; and comprehensively analyzing the determined correct path for every data input during a pre-set period of time, taking the correct path which has the largest number of occurrences as a final correct path, and outputting data in the path.

公开(公告)号：US10200042B2

公开(公告)日：2019-02-05

申请号：US15519241

申请日：2015-04-14

Applicant: SANECHIPS TECHNOLOGY CO., LTD.

Inventor： Hailiang Cui

IPC: H03K19/0185 ,  H03K19/0175 ,  H03K3/356

Abstract: Provided is an IO interface level shift circuit, comprising: an intermediate level generation circuit (11) and a level shift circuit (12). The intermediate level generation circuit is configured to provide an intermediate level Vdd_io of an IO interface. The level shift circuit is configured to convert an external logical signal into a signal in an internal power domain of a chip according to the intermediate level Vdd_io of the IO interface. Also provided are an IO interface level shift method and a storage medium. The interface level shift circuit enables level shift on an external IO signal at any level in a voltage withstanding domain of a device without adding a power domain suitable for an external IO level in the circuit.

公开(公告)号：US10172093B2

公开(公告)日：2019-01-01

申请号：US15545035

申请日：2015-07-22

Applicant: Sanechips Technology Co., Ltd.

Inventor： Yan Li ,  Junling Zhang

IPC: H04W52/02

Abstract: Disclosed is a closed-loop clock calibration method, comprising: performing clock calibration according to a calibration factor of an nth calibration period within the nth calibration period, and obtaining a calibration error of the nth calibration period; and according to the calibration error and calibration factor of the nth calibration period, obtaining a calibration factor of an (n+1)th calibration period, n being a positive integer. Also disclosed are a terminal and a computer storage medium.

公开(公告)号：US10135740B2

公开(公告)日：2018-11-20

申请号：US15301323

申请日：2014-09-22

Applicant: Sanechips Technology Co.,Ltd.

Inventor： Junjie Yin ,  Hongguang Pang

IPC: H04L12/819 ,  H04L12/26 ,  H04L12/801 ,  H04L12/851

Abstract: Provided is a token-bucket-based rate limiting method and apparatus, and a computer storage medium. The method includes that: network node equipment acquires a token bucket parameter according to an attribute of a message, then obtains a current token amount according to a time threshold and the token bucket parameter, compares the current token amount with a current message length, and processes the message according to a comparison result.

公开(公告)号：US20180181481A1

公开(公告)日：2018-06-28

申请号：US15738817

申请日：2016-05-10

Applicant: Sanechips Technology Co., Ltd.

Inventor： Feng Zhou ,  Kang An ,  Zhizhong Wang ,  Hengqi Liu

IPC: G06F11/36

CPC classification number: G06F11/364

Abstract: A method and device for realizing a snapshot function of a micro-engine processing packet intermediate data, and a computer storage medium. The method comprises: completing a snapshot of packet intermediate data via a debugging instruction to obtain packet snapshot data; completing the storage and outputting of the packet snapshot data according to a software command, so as to move and store the packet snapshot data in an external memory outside the micro-engine; and completing the bus-out of the packet snapshot data in the external memory.

公开(公告)号：US20180165250A1

公开(公告)日：2018-06-14

申请号：US15561980

申请日：2016-06-12

Applicant: Sanechips Technology Co., Ltd.

Inventor： Lan LIU ,  Chen CHENG ,  Yujiao CUI ,  Wei ZHANG ,  Yanyan ZHAO

IPC: G06F17/14

CPC classification number: G06F17/142 ,  G06F17/14 ,  H04B3/542

Abstract: A method for processing data based on 3072-point Fast Fourier Transform (FFT) and a processor based on 3072-point FFT are provided. The method for processing data based on 3072-point FFT includes: storing 3072-point data into a data storage module according to a predetermined mapping relationship (101); reading 16 data in parallel from the data storage module for performing 3-point DFT operation, and storing results into the data storage module in situ after completion of the operation (102); and reading 32 data in parallel from the data storage module for performing 1024-point DFT operation and storing results into the data storage module in situ after completion of the operation until the FFT of 3072-point data is completed (103).

公开(公告)号：US20180145912A1

公开(公告)日：2018-05-24

申请号：US15519666

申请日：2015-04-09

Applicant: Sanechips Technology Co.,Ltd.

Inventor： Min Zeng ,  Liuqin Xie ,  Youliang Zhang ,  Hengqi Liu

IPC: H04L12/801

CPC classification number: H04L47/12 ,  H04L45/125 ,  H04L49/15 ,  H04L49/1515

Abstract: Disclosed are a link control method and apparatus. The method includes that: link information and/or machine frame information in a system is acquired; and link control is performed according to the acquired link information and/or machine frame information. According to the technical solutions described in the disclosure, the problems of local congestion and packet loss in a three-level asymmetrical switching system can be effectively solved, the traffic level of the system is ensured, and the performance of the system is improved.

公开(公告)号：US20180138922A1

公开(公告)日：2018-05-17

申请号：US15574718

申请日：2016-06-01

Applicant: Sanechips Technology Co., Ltd.

Inventor： Xinliang Liu

IPC: H03M13/09 ,  H04B17/30 ,  H03K5/13

Abstract: Disclosed in the embodiments of the disclosure are a transmission checking method, node, system and computer storage medium. The method comprises: transmitting, by a SERializer/DESerializer (SERDES) transmitter, a first synchronization frame to a SERDES receiver; after the SERDES receiver receives the first synchronization frame, transmitting a second synchronization frame to the SERDES transmitter; and after the SERDES transmitter receives the second synchronization frame, transmitting a third synchronization frame to the SERDES receiver, such that the SERDES transmitter and the SERDES receiver can determine that a transmitting path and a receiving path of the SERDES transmitter and the SERDES receiver are in a normal state respectively.