公开(公告)号：US06307806B1

公开(公告)日：2001-10-23

申请号：US09652162

申请日：2000-08-31

申请人： Hiroyoshi Tomita ,  Naoharu Shinozaki

发明人： Hiroyoshi Tomita ,  Naoharu Shinozaki

IPC分类号： G11C800

CPC分类号： G11C7/1018 ,  G11C8/18 ,  G11C11/4082 ,  G11C29/78

摘要： A command receiving circuit receives a command signal for determining a circuit operation, in synchronization with a clock signal and it outputs the received command signal as an internal command signal. An address switching circuit permits transmission of an address signal to an internal circuit upon receiving the command signal. The internal circuit receives the address signal before the reception of the command signal, thereby to start its operation. As a result, the internal circuit can be operated at high speed. Besides, the address switching circuit inhibits the transmission of the address signal to the internal circuit upon receiving the internal command signal or the clock signal. Therefore, even when the level of the address signal has changed after the reception of the command signal, the change does not lead to operating the internal circuit. Accordingly, the power consumption of the semiconductor integrated circuit is reduced. Meanwhile, the semiconductor integrated circuit comprises a plurality of memory cores and a bank switch for selecting the memory cores. The bank switch feeds the address signal to predetermined memory core(s) of the memory cores in accordance with the value of the address signal. Since the memory core can receive the address signal before the validation of a command, the circuit operation is performed at high speed even in the semiconductor integrated circuit including the plurality of memory cores are controlled as bank.

摘要翻译： 命令接收电路与时钟信号同步地接收用于确定电路操作的命令信号，并且将所接收的命令信号作为内部命令信号输出。 地址切换电路允许在接收到命令信号时将地址信号发送到内部电路。 内部电路在接收到命令信号之前接收地址信号，从而开始其操作。 因此，内部电路可以高速运转。 此外，地址切换电路在接收到内部命令信号或时钟信号时，禁止向内部电路发送地址信号。 因此，即使在接收到指令信号之后地址信号的电平变化，也不会导致内部电路的工作。 因此，半导体集成电路的功耗降低。 同时，半导体集成电路包括多个存储器核和用于选择存储器核的组开关。 存储体交换机根据地址信号的值将存储器核心的地址信号提供给预定的存储器核心。 由于存储核心可以在命令验证之前接收地址信号，所以即使在包括多个存储器核心的半导体集成电路被控制为存储体的情况下，电路操作也以高速执行。

公开(公告)号：US06208582B1

公开(公告)日：2001-03-27

申请号：US09304518

申请日：1999-05-04

申请人： Tatsuya Kanda ,  Hiroyoshi Tomita

发明人： Tatsuya Kanda ,  Hiroyoshi Tomita

IPC分类号： G11C800

CPC分类号： G11C7/1096 ,  G11C7/1006 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078

摘要： A memory device, which writes data upon receiving a write command and reads data upon receiving a read command, comprises: a data input/output circuit for inputting and outputting the data in synchronization with first and second edges of a clock; and a cell array including a plurality of memory cells which store the data are. The memory device includes two sets of data bus lines connected to the cell array via column gates, a serial/parallel converter for inputting and outputting first and second write data, and two write amplifiers for driving the two data bus lines in accordance with the first and the second write data from the serial/parallel converter. The write amplifiers are activated in a write enabled state and the write amplifier is deactivated in response to a data mask signal despite being in the write enable state. The memory device has a column decoder which selects the column gate, and is inhibited the activation in response to the data mask signal. Therefore, the write-interrupt-read operation can appropriately be performed for a memory device which is compatible with the double data rate.

摘要翻译： 一种存储装置，其在接收到写入命令时写入数据并在接收到读取命令时读取数据，包括：数据输入/输出电路，用于与时钟的第一和第二边沿同步地输入和输出数据; 并且包括存储数据的多个存储单元的单元阵列。 存储器件包括通过列门连接到单元阵列的两组数据总线，用于输入和输出第一和第二写入数据的串行/并行转换器，以及用于根据第一个数据总线驱动两个数据总线的两个写入放大器 和来自串行/并行转换器的第二个写入数据。 写入放大器在写使能状态下被激活，并且写入放大器响应于数据掩码信号被去激活，尽管处于写使能状态。 存储器件具有列解码器，其选择列门，并且响应于数据掩码信号而禁止激活。 因此，对于与双倍数据速率兼容的存储器件，可以适当地执行写入中断读取操作。

公开(公告)号：US06205082B1

公开(公告)日：2001-03-20

申请号：US09304589

申请日：1999-05-04

申请人： Hiroyoshi Tomita ,  Yasurou Matsuzaki ,  Masao Taguchi

发明人： Hiroyoshi Tomita ,  Yasurou Matsuzaki ,  Masao Taguchi

IPC分类号： G11C800

CPC分类号： G11C7/1084 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22 ,  G11C2207/105 ,  G11C2207/108 ,  H01L24/45 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/00

摘要： A data signal is output from an output circuit of a first chip and sent to a data input terminal in the second chip via a data lead line based on an output clock in first chip, which is sent to the second chip. And an input circuit in a second chip receives the data signal and transfers it inside in response to a transfer clock that has been generated from the output clock in the first chip. In synchronism with a single reference clock in the first chip, therefore, a data signal can be transferred to the second chip from the first chip at a high speed.

摘要翻译： 数据信号从第一芯片的输出电路输出，并经由数据引线，基于第一芯片中的输出时钟发送到第二芯片中的数据输入端子，该输出时钟发送到第二芯片。 并且第二芯片中的输入电路响应于从第一芯片中的输出时钟产生的传输时钟，接收数据信号并将其传送到内部。 因此，与第一芯片中的单个参考时钟同步，数据信号可以从第一芯片高速传输到第二芯片。

公开(公告)号：US6144614A

公开(公告)日：2000-11-07

申请号：US353364

申请日：1999-07-15

申请人： Tatsuya Kanda ,  Hiroyoshi Tomita

发明人： Tatsuya Kanda ,  Hiroyoshi Tomita

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C8/00

CPC分类号： G11C7/225 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22

摘要： A semiconductor integrated circuit includes an internal clock generating circuit generating an internal clock, and a flip-flop circuit configured so that n latch circuits are cascaded via switch circuits performing switching operations in synchronism with the internal clock where n is an integer equal to or greater than 2. An initialization control circuit is provided so that it applies, after power on, an initialization signal to the flip-flop circuit whereby a first latch circuit among the n latch circuits is initialized. The initialization control circuit causes the internal clock generating circuit to generate the internal clock during a predetermined period so that the second through nth latch circuits are sequentially initialized.

摘要翻译： 半导体集成电路包括产生内部时钟的内部时钟发生电路和触发器电路，其配置为使得n个锁存电路经由开关电路级联，所述开关电路与内部时钟同步地执行开关操作，其中n是等于或大于等于的整数 提供初始化控制电路，使得其在上电之后将触发电路的初始化信号应用于其中，从而初始化n个锁存电路中的第一锁存电路。 初始化控制电路使得内部时钟发生电路在预定周期内产生内部时钟，使得第二到第N个锁存电路被顺序地初始化。

公开(公告)号：US6115322A

公开(公告)日：2000-09-05

申请号：US266583

申请日：1999-03-11

申请人： Tatsuya Kanda ,  Hiroyoshi Tomita

发明人： Tatsuya Kanda ,  Hiroyoshi Tomita

IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407 ,  H01L27/10 ,  G11C8/00

CPC分类号： G11C7/1078

摘要： A semiconductor device for accepting a data from outside in synchronization with data strobe signal. The semiconductor device includes control circuit for generating an accept-control signal which is activated in response to a write command inputted in synchronization with a clock signal and is inactivated in response to the data strobe signal in synchronization with the final data signal, and data input circuit for accepting the data signals while the accept-control signal is activated. The timing of the accept-control signal varies in accordance with the variation of the timing of the data strobe signal because the control circuit controls so as to inactivate the accept-control signal in response to the data strobe signal. Hence, inactivating of the accept-control signal is always performed within a predetermined time period after the final data signal is accepted in synchronization with the data strobe signal. As a result, the inactivating of the accept-control signal is accurately controlled in synchronization with the data strobe signal. Therefore, only necessary write-data are reliably accepted even if the timing of the data strobe signal varies.

摘要翻译： 一种用于从数据选通信号同步地接收外部数据的半导体器件。 半导体器件包括用于产生接收控制信号的控制电路，该接收控制信号响应于与时钟信号同步输入的写入命令被激活，并且响应于与最终数据信号同步的数据选通信号而被去激活，并且数据输入 在接受控制信号被激活时接收数据信号的电路。 接受控制信号的定时根据数据选通信号的定时的变化而变化，因为控制电路响应于数据选通信号而控制接收控制信号。 因此，在与数据选通信号同步地接受最终数据信号之后，总是在预定时间段内执行接受控制信号的失活。 结果，与数据选通信号同步地精确地控制接受控制信号的失活。 因此，即使数据选通信号的定时变化，只有必要的写入数据被可靠地接受。

公开(公告)号：US6031788A

公开(公告)日：2000-02-29

申请号：US207335

申请日：1998-12-08

申请人： Yoshihide Bando ,  Nobutaka Taniguchi ,  Hiroyoshi Tomita

发明人： Yoshihide Bando ,  Nobutaka Taniguchi ,  Hiroyoshi Tomita

IPC分类号： G11C11/407 ,  G06F1/04 ,  G11C7/10 ,  G11C7/22 ,  G11C7/00

CPC分类号： G11C7/22 ,  G11C7/1072

摘要： A semiconductor integrated circuit is adapted to make invalid an external clock, externally supplied to the semiconductor integrated circuit, when the semiconductor integrated circuit is set in an active power-down state. The semiconductor integrated circuit includes a delay locked loop DLL circuit which outputs an internal clock which phase is synchronized to the external clock. A latch circuit retains control signals in synchronism with the internal clock output by the DLL circuit. An internal circuit performs a predetermined process based on the control signals supplied from the latch circuit.

摘要翻译： 当半导体集成电路处于有功掉电状态时，半导体集成电路适于使外部提供给半导体集成电路的外部时钟无效。 半导体集成电路包括延迟锁定环DLL电路，其输出与外部时钟同步的内部时钟。 锁存电路保持与DLL电路的内部时钟输出同步的控制信号。 内部电路基于从锁存电路提供的控制信号执行预定处理。

公开(公告)号：US07808850B2

公开(公告)日：2010-10-05

申请号：US12255322

申请日：2008-10-21

申请人： Hiroyoshi Tomita

发明人： Hiroyoshi Tomita

IPC分类号： G11C29/00

CPC分类号： G11C29/12 ,  G11C2029/0405

摘要： First and second data output circuits obtain corresponding parts of read data of a storage circuit to output to first and second input/output pads in a second test mode. First and second data input circuits obtain output data of the first and second data output circuits via the first and second input/output pads to output in the second test mode. A comparison object selection circuit selects output data of the first and second data input circuits to output in the second test mode. A judging circuit performs a test judgment by comparing output data of the comparison object selection circuit with expected value data and outputs a test result signal in the second test mode.

摘要翻译： 第一和第二数据输出电路获得存储电路的读取数据的相应部分，以在第二测试模式下输出到第一和第二输入/输出焊盘。 第一和第二数据输入电路经由第一和第二输入/输出焊盘获得第一和第二数据输出电路的输出数据，以在第二测试模式下输出。 比较对象选择电路选择第一和第二数据输入电路的输出数据，以在第二测试模式下输出。 判断电路通过将比较对象选择电路的输出数据与期望值数据进行比较来进行测试判断，并在第二测试模式中输出测试结果信号。

公开(公告)号：US07548465B2

公开(公告)日：2009-06-16

申请号：US12054961

申请日：2008-03-25

申请人： Shusaku Yamaguchi ,  Hiroyoshi Tomita

发明人： Shusaku Yamaguchi ,  Hiroyoshi Tomita

IPC分类号： G11C7/00

CPC分类号： G11C7/1006 ,  G11C7/1078 ,  G11C7/1087 ,  G11C11/4076

摘要： A semiconductor memory device that includes an input buffer being inputted a write data from outside to buffer the write data and a control circuit putting the input buffer into an inactive state during a read operation and putting the input buffer into an active state when a read mask signal is inputted thereafter is provided.

摘要翻译： 一种半导体存储器件，包括从外部输入写入数据以缓冲写入数据的输入缓冲器以及在读取操作期间将输入缓冲器置于非活动状态的控制电路，并且当读取掩模 之后输入信号。

公开(公告)号：US07545699B2

公开(公告)日：2009-06-09

申请号：US11892497

申请日：2007-08-23

申请人： Hiroyoshi Tomita

发明人： Hiroyoshi Tomita

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C5/143 ,  G11C7/1045 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/4074

摘要： A semiconductor memory device includes a timing signal circuit to generate a refresh timing signal comprised of a series of pulses, a refresh address circuit to generate a refresh address in synchronization with each pulse of the refresh timing signal, a pulse selecting circuit to assert a refresh request signal in synchronization with pulses selected from the series of pulses, and a memory core to receive the refresh address and the refresh request signal and to perform a refresh operation with respect to the refresh address in response to assertion of the refresh request signal, wherein arrangement is made to switch between a first operation mode in which the selected pulses are obtained by selecting one pulse out of every predetermined number of pulses from the series of pulses and a second operation mode in which the selected pulses are obtained by selecting consecutive pulses from the series of pulses.

摘要翻译： 半导体存储器件包括：定时信号电路，用于产生由一系列脉冲组成的刷新定时信号;刷新地址电路，用于与刷新定时信号的每个脉冲同步产生刷新地址;脉冲选择电路，用于断言刷新 请求信号与从一系列脉冲中选择的脉冲同步;以及存储器核，用于接收刷新地址和刷新请求信号，并响应于刷新请求信号的断言而对刷新地址执行刷新操作，其中 通过从脉冲串中选出每一个预定数量的脉冲中的一个脉冲和第二操作模式，在第一操作模式和第二操作模式之间切换选择的脉冲的第一操作模式，其中通过从 一系列脉冲。

公开(公告)号：US20090040852A1

公开(公告)日：2009-02-12

申请号：US12255322

申请日：2008-10-21

申请人： Hiroyoshi TOMITA

发明人： Hiroyoshi TOMITA

IPC分类号： G11C29/00

CPC分类号： G11C29/12 ,  G11C2029/0405

摘要： First and second data output circuits obtain corresponding parts of read data of a storage circuit to output to first and second input/output pads in a second test mode. First and second data input circuits obtain output data of the first and second data output circuits via the first and second input/output pads to output in the second test mode. A comparison object selection circuit selects output data of the first and second data input circuits to output in the second test mode. A judging circuit performs a test judgment by comparing output data of the comparison object selection circuit with expected value data and outputs a test result signal in the second test mode.

摘要翻译： 第一和第二数据输出电路获得存储电路的读取数据的相应部分，以在第二测试模式下输出到第一和第二输入/输出焊盘。 第一和第二数据输入电路经由第一和第二输入/输出焊盘获得第一和第二数据输出电路的输出数据，以在第二测试模式下输出。 比较对象选择电路选择第一和第二数据输入电路的输出数据，以在第二测试模式下输出。 判断电路通过将比较对象选择电路的输出数据与期望值数据进行比较来进行测试判断，并在第二测试模式中输出测试结果信号。