公开(公告)号：US20080189478A1

公开(公告)日：2008-08-07

申请号：US12021395

申请日：2008-01-29

Applicant: Dong-Hyuk CHAE ,  Young-Ho LIM

Inventor： Dong-Hyuk CHAE ,  Young-Ho LIM

IPC: G06F12/02 ,  G06F12/08

CPC classification number: G06F12/0246 ,  G06F2212/7203

Abstract: A nonvolatile semiconductor memory device for an efficient program of multilevel data includes a memory cell array having a plurality of banks and a cache block corresponding to each of the plurality of banks. The cache block has a predetermined data storage capacity. A page buffer is included which corresponds to each of the plurality of banks. A programming circuit programs all of the plurality of banks except a last of said banks with page data. The page data is loaded through each page buffer and programmed into each cache block such that when page data for the last bank is loaded into the page buffer, the loaded page data and the page data programmed into the respective cache blocks are programmed into respective corresponding banks. Accordingly, the time taken in programming can be reduced without increasing a unit of program in a multilevel flash memory, thereby improving performance in a multilevel program of a nonvolatile semiconductor memory device.

Abstract translation: 用于多电平数据的高效程序的非易失性半导体存储器件包括具有多个存储体的存储单元阵列和与多个存储体中的每一个对应的高速缓存块。 高速缓存块具有预定的数据存储容量。 包括对应于多个存储体中的每一个的页缓冲器。 编程电路使用页面数据对除了最后的所述存储体之外的所有多个存储体进行编程。 页面数据通过每个页面缓冲器加载并被编程到每个缓存块中，使得当最后一个存储体的页面数据被加载到页面缓冲器中时，加载的页面数据和编入各个缓存块中的页面数据被编程到相应的对应的 银行。 因此，可以在不增加多级闪存中的程序单元的情况下减少编程所花费的时间，从而提高非易失性半导体存储器件的多级程序中的性能。

公开(公告)号：US07403429B2

公开(公告)日：2008-07-22

申请号：US11548630

申请日：2006-10-11

Applicant: Dong-Hyuk Chae ,  Young-Ho Lim

Inventor： Dong-Hyuk Chae ,  Young-Ho Lim

IPC: G11C11/34

CPC classification number: G11C16/16 ,  G11C16/08

Abstract: A method of erasing data in a nonvolatile semiconductor memory device including applying an erase voltage to a substrate of the semiconductor memory device, applying a ground voltage to wordlines of a selected memory cell string formed in the substrate, and applying a control voltage to at least one of a string selection line and a ground selection line of the selected memory cell string.

Abstract translation: 一种擦除非易失性半导体存储器件中的数据的方法，包括向半导体存储器件的衬底施加擦除电压，将接地电压施加到形成在衬底中的所选择的存储器单元串的字线，并将控制电压施加至少 选择的存储单元串的字符串选择行和地选择行之一。

公开(公告)号：US07379333B2

公开(公告)日：2008-05-27

申请号：US11228189

申请日：2005-09-19

Applicant: Sung-Soo Lee ,  Young-Ho Lim ,  Hyun-Chul Cho ,  Dong-Hyuk Chae

Inventor： Sung-Soo Lee ,  Young-Ho Lim ,  Hyun-Chul Cho ,  Dong-Hyuk Chae

IPC: G11C11/34

CPC classification number: G11C16/0483 ,  G11C16/26

Abstract: In one aspect, a non-volatile memory device is provided which is operable in a programming mode and a read mode. The memory device includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit lines. The memory device further includes an internal data output line for outputting data read from the bit lines of the memory array, and a page buffer operatively connected between a bit line of the memory cell array and the internal data output line. The page buffer includes a sense node which is selectively connected to the bit line, a latch circuit having a latch node which is selectively connected to the sense node, a latch input path which sets a logic voltage of the latch node in the programming mode and the read mode, and a latch output path which is separate from the latch input path and which sets as logic voltage of the internal date output line according to the logic voltage of the latch node.

Abstract translation: 在一个方面，提供一种可在编程模式和读取模式下操作的非易失性存储器件。 存储器件包括存储单元阵列，其包括多个非易失性存储器单元，多个字线和多个位线。 存储器件还包括用于输出从存储器阵列的位线读取的数据的内部数据输出线以及可操作地连接在存储单元阵列的位线和内部数据输出线之间的页缓冲器。 页面缓冲器包括选择性地连接到位线的感测节点，具有选择性地连接到感测节点的锁存节点的锁存电路，将锁存节点的逻辑电压设置为编程模式的锁存器输入路径，以及 读取模式和与锁存器输入路径分离并根据锁存节点的逻辑电压设置为内部日期输出线的逻辑电压的锁存器输出路径。

公开(公告)号：US20080019183A1

公开(公告)日：2008-01-24

申请号：US11833546

申请日：2007-08-03

Applicant: Dong-Hyuk Chae ,  Dae-Seok Byeon

Inventor： Dong-Hyuk Chae ,  Dae-Seok Byeon

IPC: G11C16/02

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/08

Abstract: Flash memory devices include a memory array having a plurality of NAND strings of EEPROM cells therein. A word line driver is provided to improve programming efficiency. The word line driver is electrically coupled to the memory array by a plurality of word lines. The word line driver includes a plurality of pass voltage switches. These switches have outputs electrically coupled by diodes to the plurality of word lines. Methods of programming flash memory devices include applying a pass voltage to a plurality of unselected word lines in a non-volatile memory array while simultaneously applying a sequentially ramped program voltage to a selected word line in the non-volatile memory array. The sequentially ramped program voltage has a minimum value that is clamped by a word line driver to a level not less than a value of the pass voltage.

Abstract translation: 闪存器件包括其中具有多个EEPROM串的NAND串的存储器阵列。 提供字线驱动程序以提高编程效率。 字线驱动器通过多个字线电耦合到存储器阵列。 字线驱动器包括多个通过电压开关。 这些开关具有由二极管电耦合到多个字线的输出。 编程闪速存储器件的方法包括在非易失性存储器阵列中向多个未选择的字线施加通过电压，同时将顺序斜坡的编程电压施加到非易失性存储器阵列中的选定字线。 顺序斜坡编程电压具有被字线驱动器钳位到不小于通过电压值的电平的最小值。

公开(公告)号：US07298648B2

公开(公告)日：2007-11-20

申请号：US11228194

申请日：2005-09-19

Applicant: Sung-Soo Lee ,  Young-Ho Lim ,  Hyun-Chul Cho ,  Dong-Hyuk Chae

Inventor： Sung-Soo Lee ,  Young-Ho Lim ,  Hyun-Chul Cho ,  Dong-Hyuk Chae

IPC: G11C16/04

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C2211/5642

Abstract: According to one aspect, a memory cell array includes a bit line connected to a plurality of nonvolatile memory cells, where the nonvolatile memory cells are selectively programmable in any one of at least first, second, third and fourth threshold voltage states, and where the first, second, third and fourth threshold voltage states correspond to four different data values defined by first and second bits. A page buffer circuit stores a logic value as main latch data and is responsive to a main latch signal to selectively flip the logic value of the main latch data according to a voltage level of the bit line. A sub-latch circuit stores a logic value as sub-latch data and is responsive to a sub-latch signal to selectively flip the logic value of the sub-latch data according to the voltage level of the bit line. The memory device is operable in a read mode which reads the threshold voltage state of the non-volatile memory cells and a programming mode which programs the threshold voltage state of the non-volatile memory cells, wherein the page buffer circuit is selectively responsive to the sub-latch data to inhibit flipping of the logic value of the main latch data in the programming mode.

Abstract translation: 根据一个方面，存储单元阵列包括连接到多个非易失性存储单元的位线，其中非易失性存储单元可选择性地以至少第一，第二，第三和第四阈值电压状态中的任何一个编程，并且其中 第一，第二，第三和第四阈值电压状态对应于由第一和第二位定义的四个不同的数据值。 页面缓冲电路将逻辑值存储为主锁存数据，并且响应于主锁存信号，以根据位线的电压电平选择性地翻转主锁存数据的逻辑值。 子锁存电路将逻辑值存储为子锁存数据，并且响应于子锁存信号，以根据位线的电压电平选择性地翻转子锁存数据的逻辑值。 存储器件可读取读取非易失性存储器单元的阈值电压状态的读取模式和编程非易失性存储器单元的阈值电压状态的编程模式，其中页面缓冲器电路有选择地响应于 子锁存数据，以禁止在编程模式下翻转主锁存器数据的逻辑值。

公开(公告)号：US20070133305A1

公开(公告)日：2007-06-14

申请号：US11548630

申请日：2006-10-11

Applicant: Dong-Hyuk CHAE ,  Young-Ho LIM

Inventor： Dong-Hyuk CHAE ,  Young-Ho LIM

IPC: G11C16/04

CPC classification number: G11C16/16 ,  G11C16/08

Abstract: A method of erasing data in a nonvolatile semiconductor memory device including applying an erase voltage to a substrate of the semiconductor memory device, applying a ground voltage to wordlines of a selected memory cell string formed in the substrate, and applying a control voltage to at least one of a string selection line and a ground selection line of the selected memory cell string.

Abstract translation: 一种擦除非易失性半导体存储器件中的数据的方法，包括向半导体存储器件的衬底施加擦除电压，将接地电压施加到形成在衬底中的所选择的存储器单元串的字线，并将控制电压施加至少 选择的存储单元串的字符串选择行和地选择行之一。

公开(公告)号：US20060291293A1

公开(公告)日：2006-12-28

申请号：US11320096

申请日：2005-12-28

Applicant: Dong-Hyuk Chae ,  Young-Ho Lim

Inventor： Dong-Hyuk Chae ,  Young-Ho Lim

IPC: G11C11/34

CPC classification number: G11C8/08 ,  G11C16/349

Abstract: A non-volatile semiconductor memory device includes: cell strings connected to respective bit lines; each of the cell strings having a string select transistor connected to a string select line, a ground select transistor connected to a ground select line, and memory cells connected to corresponding word lines and connected in series between the string select transistor and the ground select transistor; a first voltage drop circuit configured to reduce an applied read voltage during a read operation; a second voltage drop circuit configured to reduce the applied read voltage; a string select line driver circuit configured to drive the string select line with the reduced voltage provided by the first voltage drop circuit; and a ground select line driver circuit configured to drive a ground select line with the reduced voltage provided by the second voltage drop circuit.

Abstract translation: 非易失性半导体存储器件包括：连接到相应位线的单元串; 每个单元串具有连接到串选择线的串选择晶体管，连接到接地选择线的接地选择晶体管和连接到对应字线并且串联连接在串选择晶体管和接地选择晶体管之间的存储单元 ; 第一电压降电路，被配置为在读取操作期间减小施加的读取电压; 配置为减小所施加的读取电压的第二电压降电路; 串行选择线驱动电路，被配置为利用由第一压降电路提供的降低的电压驱动串选择线; 以及接地选择线驱动电路，被配置为用由第二压降电路提供的降低的电压来驱动接地选择线。

公开(公告)号：US07072238B2

公开(公告)日：2006-07-04

申请号：US11025001

申请日：2004-12-28

Applicant: Dong-Hyuk Chae ,  Young-Ho Lim

Inventor： Dong-Hyuk Chae ,  Young-Ho Lim

IPC: G11C7/00

CPC classification number: G11C5/145 ,  G11C16/30

Abstract: A semiconductor device that generates a regulated high voltage. The device includes, a high voltage generation circuit for supplying a high voltage to the first power line, a current bypass circuit for supplying current to a second power line from the first power line, a PMOS transistor coupled between a first power line and the second power line, and a controller for controlling the drive current of the PMOS transistor in response to the voltage on the second power line.

Abstract translation: 一种产生稳压高电压的半导体器件。 该装置包括用于向第一电力线提供高电压的高电压产生电路，用于从第一电力线向第二电力线提供电流的电流旁路电路，耦合在第一电力线和第二电力线之间的PMOS晶体管 电源线和用于响应于第二电力线上的电压来控制PMOS晶体管的驱动电流的控制器。

公开(公告)号：US20060044884A1

公开(公告)日：2006-03-02

申请号：US11025001

申请日：2004-12-28

Applicant: Dong-Hyuk Chae ,  Young-Ho Lim

Inventor： Dong-Hyuk Chae ,  Young-Ho Lim

IPC: G11C5/14

CPC classification number: G11C5/145 ,  G11C16/30

Abstract: A semiconductor device that generates a regulated high voltage. The device includes, a high voltage generation circuit for supplying a high voltage to the first power line, a current bypass circuit for supplying current to a second power line from the first power line, a PMOS transistor coupled between a first power line and the second power line, and a controller for controlling the drive current of the PMOS transistor in response to the voltage on the second power line.

Abstract translation: 一种产生稳压高电压的半导体器件。 该装置包括用于向第一电力线提供高电压的高电压产生电路，用于从第一电力线向第二电力线提供电流的电流旁路电路，耦合在第一电力线和第二电力线之间的PMOS晶体管 电源线和用于响应于第二电力线上的电压来控制PMOS晶体管的驱动电流的控制器。

公开(公告)号：US08339846B2

公开(公告)日：2012-12-25

申请号：US12856698

申请日：2010-08-16

Applicant: Hee-seok Eun ,  Jong-han Kim ,  Jae-hong Kim ,  Dong-hyuk Chae ,  Seung-hwan Song ,  Han-woong Yoo ,  Jun-jin Kong ,  Young-hwan Lee ,  Kyoung-lae Cho ,  Yong-june Kim

Inventor： Hee-seok Eun ,  Jong-han Kim ,  Jae-hong Kim ,  Dong-hyuk Chae ,  Seung-hwan Song ,  Han-woong Yoo ,  Jun-jin Kong ,  Young-hwan Lee ,  Kyoung-lae Cho ,  Yong-june Kim

IPC: G11C16/04

CPC classification number: G11C11/5628 ,  G11C11/5642

Abstract: The flash memory device includes a control logic circuit and a bit level conversion logic circuit. The control logic circuit programs first through Nth bits of data in a memory cell array of the N-bit MLC flash memory device or reads the first through Nth bits of the data from the memory cell array in response to one of a program command and a read command. The bit level conversion control logic circuit, after the first through Nth bits of the data are completely programmed or read, programs or reads an (N+1)th bit of the data in response to a control signal. The bit level conversion control logic circuit converts voltage levels of voltages, which are used for programming or reading the first through Nth bits of the data, to program or read for 2N cell distributions of 2N+1 cell distributions corresponding to the (N+1)th bit of the data and then programs or reads for other 2N cell distributions.

Abstract translation: 闪存器件包括控制逻辑电路和位电平转换逻辑电路。 控制逻辑电路对N位MLC闪速存储器件的存储单元阵列中的第一至第N位数据进行编程，或响应于程序命令和程序命令之一从存储单元阵列中读取数据的第一至第N位 读命令。 在数据的第一至第N位被完全编程或读取之后，位电平转换控制逻辑电路响应于控制信号编程或读取数据的第（N + 1）位。 位电平转换控制逻辑电路转换用于编程或读取数据的第一至第N位的电压电平，以对与第（N + 1）个对应的2N + 1个单元分布的2N个单元分布进行编程或读取 ）位，然后编程或读取其他2N个单元分布。