公开(公告)号：US20230099170A1

公开(公告)日：2023-03-30

申请号：US17449217

申请日：2021-09-28

Applicant: Red Hat, Inc.

Inventor： Michael Tsirkin ,  Andrea Arcangeli ,  Giuseppe Scrivano

IPC: G06F12/0804 ,  G06F9/50 ,  G06F9/455

Abstract: An example system includes a memory, a processor in communication with the memory, and a supervisor. The supervisor is configured to allocate a memory space in the memory to a workload executing on the processor. The supervisor is configured to store data written by the workload as dirty memory in the memory space at least until the data is written back to a data storage. Based on a type of the workload being a first type, the supervisor is configured to trigger write back of at least a portion of the dirty memory into the data storage in response to the dirty memory exceeding a threshold level. Based on the type of the workload being a second type, the supervisor is configured to delay write back of the dirty memory into the data storage in response to the dirty memory exceeding the threshold level.

公开(公告)号：US11614997B2

公开(公告)日：2023-03-28

申请号：US17306896

申请日：2021-05-03

Applicant: PHISON ELECTRONICS CORP.

Inventor： Hsiao-Chi Ho

IPC: G06F11/14 ,  G06F11/10 ,  G06F11/07 ,  G06F11/16 ,  G06F12/0804 ,  G06F12/0866 ,  G06F3/06

Abstract: A method for managing a host memory buffer, a memory storage apparatus, and a memory control circuit unit are provided. The method includes: detecting whether a system abnormality occurs; copying a first command and first data corresponding to the first command stored in a data buffer of a host system to the memory storage apparatus in response to determining that the system abnormality occurs; executing an initial operation after copying the first command and the first data, wherein the initial operation initializes a part of a hardware circuit in the memory storage apparatus and does not initialize another part of the hardware circuit in the memory storage apparatus; and re-executing the first command stored in the memory storage apparatus after initializing the part of the hardware circuit.

公开(公告)号：US11614889B2

公开(公告)日：2023-03-28

申请号：US16205094

申请日：2018-11-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Christopher J. Brennan

IPC: G06F3/06 ,  G06F12/0804

Abstract: An operation combiner receives a series of commands with read addresses, a modification operation, and write addresses. In some cases, the commands have serial dependencies that limit the rate at which they can be processed. The operation combiner compares the addresses for compatibility, transforms the operations to break serial dependencies, and combines multiple source commands into a smaller number of aggregate commands that can be executed much faster than the source commands. Some embodiments of the operation combiner receive a first command including one or more first read addresses and a first write address. The operation combiner compares the first read addresses and the first write address to one or more second read addresses and a second write address of a second command stored in a buffer. The operation combiner selectively combines the first and second commands to form an aggregate command based on the comparison.

公开(公告)号：US11604736B2

公开(公告)日：2023-03-14

申请号：US17253981

申请日：2020-10-30

Applicant: SHENZHEN CHUANGWEI-RGB ELECTRONICS CO., LTD.

Inventor： Jiayin Fu ,  Shanhui Tian

IPC: G06F12/0891 ,  G06F12/02 ,  G06F12/0804

Abstract: The present disclosure provides a memory cleaning method, a smart terminal, and a readable storage medium. When the smart terminal is switched from a first display state to a second display state, an application to be cleaned is determined. A space to be cleaned is determined from a running memory and cache space occupied during running of the application to be cleaned. Files are removed from each of the determined spaces to be cleaned. In this way, an application to be cleaned is determined when the smart terminal is switched from a first display state to a second display state, so that an application to be cleaned can be directly cleaned in the background, and applications can be cleaned in real time without affecting the user's normal operation, which contributes to more timely cleaning of applications and an improved user experience.

公开(公告)号：US20230076729A2

公开(公告)日：2023-03-09

申请号：US17421800

申请日：2020-01-09

Applicant: ZEROPOINT TECHNOLOGIES AB

Inventor： Angelos Arelakis ,  Per Stenström

IPC: G06F16/215 ,  G06F16/22 ,  G06F12/0804

Abstract: A computer memory compression method involves analyzing (1210) computer memory content with respect to occurrence of duplicate memory objects as well as value redundancy of data values in unique memory objects. The computer memory content is encoded (1220) by eliminating the duplicate memory objects and compressing each remaining unique memory object by exploiting data value locality of the data values thereof. Metadata (500) is provided (1230) to represent the memory objects of the encoded computer memory content. The metadata reflects eliminated duplicate memory objects, remaining unique memory objects as well as a type of compression used for compressing each remaining unique memory object. A memory object in the encoded computer memory content is located (1240) using the metadata (500).

公开(公告)号：US11599466B2

公开(公告)日：2023-03-07

申请号：US17704561

申请日：2022-03-25

Applicant: Micron Technology, Inc.

Inventor： Robert M. Walker ,  Ashay Narsale

IPC: G06F12/0804 ,  G06F12/12

Abstract: Exemplary methods, apparatuses, and systems include identifying that a first cache line from a first cache is subject to an operation that copies data from the first cache to a non-volatile memory. A first portion of the first cache line stores clean data and a second portion of the first cache line stores dirty data. A redundant copy of the dirty data is stored in a second cache line of the first cache. In response to identifying that the first cache line is subject to the operation, metadata associated with the redundant copy of the dirty data is used to copy the dirty data to a non-volatile memory while omitting the clean data.

公开(公告)号：US11599464B2

公开(公告)日：2023-03-07

申请号：US16995567

申请日：2020-08-17

Applicant: SK hynix Inc.

Inventor： Do Hun Kim

IPC: G06F12/00 ,  G06F12/0804

Abstract: An electronic device includes a memory controller having an improved operation speed. The memory controller includes a main memory, a processor configured to generate commands for accessing data stored in the main memory, a scheduler configured to store the commands and output the commands according to a preset criterion, a cache memory configured to cache and store data accessed by the processor among the data stored in the main memory, and a hazard filter configured to store information on an address of the main memory corresponding to a write command among the commands, provide a pre-completion response for the write command to the scheduler upon receiving the write command, and provide the write command to the main memory.

公开(公告)号：US11599463B2

公开(公告)日：2023-03-07

申请号：US16829554

申请日：2020-03-25

Applicant: Ocient Holdings LLC

Inventor： George Kondiles ,  Jason Arnold ,  S. Christopher Gladwin ,  Joseph Jablonski ,  Daniel Coombs ,  Andrew D. Baptist

IPC: G06F12/08 ,  G06F12/0804 ,  G06F16/22 ,  G06F16/2455

Abstract: A method for execution by a temporary ingress storage system includes receiving a set of records to be processed for long-term storage. The set of records are temporarily stored in a set of memory resources of the temporary ingress storage system during a first temporal period. Execution of a query is facilitated by accessing a subset of the set of records from at least one memory resource of the set of memory resources during the first temporal period. The set of records are processed to generate a set of segments for long-term storage. Migration of the set of records from the temporary ingress storage system to a long-term storage system for during a second temporal period that begins after the first temporal period has elapsed by sending the set of records to the long-term storage system.

公开(公告)号：US20230069152A1

公开(公告)日：2023-03-02

申请号：US17411792

申请日：2021-08-25

Applicant: VMware, Inc.

Inventor： Isam Wadih AKKAWI ,  Andreas NOWATZYK ,  Pratap SUBRAHMANYAM ,  Nishchay DUA ,  Adarsh Seethanadi NAYAK ,  Venkata Subhash Reddy PEDDAMALLU ,  Irina CALCIU

IPC: G06F12/0804 ,  G06F13/16 ,  G06F13/40

Abstract: In a computer system, a processor and an I/O device controller communicate with each other via a coherence interconnect and according to a cache coherence protocol. Registers of the I/O device controllers are mapped to the cache coherent memory space to allow the processor to treat the registers as cacheable memory. As a result, latency of processor commands executed by the I/O device controller is decreased, and size of data stored in the I/O device controller that can be accessed by the processor is increased from the size of a single register to the size of an entire cache line.

公开(公告)号：US11593272B2

公开(公告)日：2023-02-28

申请号：US16579988

申请日：2019-09-24

Applicant: EMC IP Holding Company LLC

Inventor： Ruiyong Jia ,  Jibing Dong ,  Baote Zhuo ,  Chun Ma ,  Jianbin Kang

IPC: G06F12/10 ,  G06F12/0804

Abstract: In response to receiving a read request for target data, an external address of the target data is obtained from the read request, which is an address unmapped to a storage system; hit information of the target data in cache of the storage system is determined based on the external address; and based on the hit information, an address from the external address and an internal address for providing the target data is determined. The internal address is determined based on the external address and a mapping relationship. Therefore, it can shorten the data access path, accelerate the responding speed for the data access request, and allow the cache to prefetch the data more efficiently.